VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8121
Features
• Monolithic Phase Locked Loop
• On-Chip LC Oscillator
• On-Chip Loop Filter
• TTL/CMOS Reference Clock
• Selectable Reference
2.488GHz SONET/SDH
Clock Generator
• Jitter Meets SONET OC-48 and
SDH STM-16 Requirements
• High-Speed CML Clock Output
• Single 3.3V Supply
• Compact 10mm x 10mm 44 Pin PQFP Package
General Description
The VSC8121 is a monolithic Phase Locked Loop (PLL) based clock generator designed for telecommuni-
cations systems operating at 2.5Gb/s. The VSC8121 incorporates a reactance-based (LC) Voltage Controlled
Oscillator (VCO) with low phase noise. The PLL’s loop filter is on-chip.
The device has a differential 2.488GHz CML clock output (CO/CON) signal, a single-ended TTL low-
speed clock (LSCLK) output equivalent in frequency to that of the reference clock, and a TTL reference clock
input selectable for 51.84MHz, 77.76MHz or 155.52MHz. TTL inputs REFSEL[0:1] are used to make this
selection.
A clean REFCLK signal is required since jitter below the PLL loop bandwidth, which is present on the
REFCLK input, will appear on the output. Jitter on REFCLK at frequencies above the loop bandwidth will be
attenuated by the PLL. The state of REFSEL[0:1] will select which frequency is expected on the REFCLK
input.
VSC8121 Functional Block Diagram
REFCLK
Ph.Freq.
Detector
Loop
Filter
VCO
CO
CON
CLOCK
OUT
LSCLK
Divider
REFSEL[0:1]
G52163-0, Rev 4.2
04/16/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
2.488GHz SONET/SDH
Clock Generator
Data Sheet
VSC8121
Applications Information
High-Speed Clock Output
The differential clock output waveforms produced by the VSC8121 are sinusoidal in nature, by design. This
typically results in less noise generation than square pulses in most customer applications. Figure 1 shows a typ-
ical, single-ended clock output waveform produced by the device.
Figure 1: Typical Clock Output (CO) Waveform
75mV/div
100ps/div
CO and CON are high-speed CML outputs. As shown in Figure 2, the output driver consists of a differential
pair designed to drive a 50
Ω
transmission line environment. Note that the output driver is back terminated to
50
Ω
on-chip to prevent reflections.
Careful layout of these signals is required for optimal performance. Figure 3 demonstrates various termina-
tion methods that may be employed, depending on the particular application. Either DC-coupling (termination
#1 in Figure 3) or one of two AC coupling methods (terminations #2 and #3) may be used. As indicated, Vitesse
recommends termination #2 for AC-coupling.
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52163-0, Rev 4.2
04/16/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8121
Figure 2: High-Speed Clock Output Diagram
V
CC
2.488GHz SONET/SDH
Clock Generator
50Ω
50Ω
CO
CON
Pre-Driver
V
EE
Figure 3: Example High-Speed CML Clock Output Terminations
1)
CO/CON
(Recommended for DC-Coupling)
V
CC
50
Ω
0.01
µf
2)
CO/CON
50
Ω
(Recommended for AC-Coupling)
V
TERM
3)
CO/CON
(Alternative for AC-Coupling)
50
Ω
0.01
µf
V
TERM
G52163-0, Rev 4.2
04/16/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
2.488GHz SONET/SDH
Clock Generator
Data Sheet
VSC8121
Reference Clock Input
The input stage at the REFCLK input pin consists of ESD protection, followed by a current limiting circuit
which precedes a driver responsible for providing the signal to the phase frequency detector. As pictured below
in Figure 4, the driver has a high impedance, FET gate input. The additional resistance contributed by the cur-
rent limiting circuit is relatively negligible.
Figure 4: Reference Clock Input Diagram
VCC
REFCLK
Current
Limiting
VTT
VEE
Care should be taken in selection of the reference clock. Time jitter on the reference clock which is within
the PLL’s loop bandwidth will appear on the 2.5GHz output. Telecom quality crystal oscillators from vendors
such as Connor-Winfield or Vectron are suitable.
Table 1: Reference Clock Selection
REFSEL[1]
0
1
Don’t Care
REFSEL[0]
0
0
1
Selected Reference
Frequency
51.84MHz
77.76MHz
155.52MHz
Typical
Loop Bandwidth
2500KHz
3000KHz
5500KHz
Die Usage
Vitesse optionally provides this device in unpackaged, die-only format for multi-chip module and related
applications. For further informtion, please contact Vitesse.
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52163-0, Rev 4.2
04/16/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8121
AC Characteristics
Table 2: AC Characteristics
Parameter
T
CLK
RC
d
RC
f
∆f
RC
t
jitter
2.488GHz SONET/SDH
Clock Generator
Description
High-speed output clock period
Reference clock duty cycle
Reference clock frequency (selectable)
Reference clock frequency tolerance
Jitter generation
Min
—
45
—
-100
—
Typ
401.9
—
51.84,
77.76,
or
155.52
—
1.75
Max
—
55
—
+100
3.6
Units
ps
%
MHz
ppm
(1)
ps RMS
Conditions
12kHz to 20MHz.
See Figure 5.
NOTE: (1) ppm refers to “parts per million.” 100ppm (100/1000000) is equivalent to 0.01%. Therefore, the equivalent reference
clock frequency range in MHz for +/-100ppm tolerance is as follows:
RC
f
51.84MHz
77.76MHz
155.52MHz
X 100ppm =
5.184KHz
7.776KHz
15.552KHz
Acceptable Range
51.83MHz to 51.85MHz
77.75MHz to 77.78MHz
155.51MHz to 155.54MHz
Note that +/-100ppm tolerance for reference clock frequency more than accommodates the SONET/SDH requirement that refer-
ence clock-supplying crystals function at +/-20ppm.)
Figure 5: RMS/Peak-to-Peak Jitter (12kHz - 20MHz), REF_CLK freq = 77.76MHz
RMS Jitter
3.0
2.5
2.0
ps
ps
Pk-Pk Jitter
25
20
15
10
5
0
1.5
1.0
0.5
0.0
0
20
40
60
80
100
0
20
40
60
80
100
Case Temperature (deg C)
Case Temperature (deg C)
G52163-0, Rev 4.2
04/16/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 5
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