D a ta S h ee t , D S 3 , Ju ly 20 0 1
DFE-Q V 2 .1
Quad ISDN 2B1Q
E c h o c a n c e l l e r D i g it a l
Front End
PE F 24 91 1 V er s io n 2 . 1
Wi re d
C om m un ic a t io ns
N e v e r
s t o p
t h i n k i n g .
Edition 2001-07-16
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 7/16/01.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a ta S h ee t , D S 3 , Ju ly 20 0 1
DFE-Q V 2 .1
Quad ISDN 2B1Q
E c h o c a n c e l l e r D i g it a l
Front End
PE F 24 91 1 V er s io n 2 . 1
Wi re d
C om m un ic a t io ns
N e v e r
s t o p
t h i n k i n g .
PEF 24911
Revision History:
Previous Version:
Page
Page 13
Page 13
Page 13,
Page 39
Page 28
Page 43
Page 54
Page 63
Page 95
Page 130
Page 97
Page 103
Page 113
Page 119
Page 120
Page 121
Page 125
Page 127
2001-07-16
Data Sheet 11.00
DS 3
DS 2
Subjects (major changes since last revision)
New function: Disable Super Frame Marker introduced on pin 16: DSFM
Refined description of pin 49: CRCON
Especially, CRCON = ’1’ selects MFILT= 0011 0xxx (erroneously, MFILT=
000010xx was documented in DS2)
Added note: MON-12 read access is impossible in state ’Deactivated’
Restriction: PACA/PACE must not be used during local loopback active
C/I-command LTD added (function as in V1.x)
AR0 and ARX set UOA = ’1’ (before: AR0 and ARX set UOA to the same
value as the received SAI bit)
Refined description ’Framer / Deframer Loopback’:
- always transparent
- prerequisite is transparent state
Bit Error Rate Counter: refined operational description
Data Through is only test mode, C/I-command = ARL must not be applied
when pin DT = ’1’
Refined description of ’Control via MON-2’
Removed ’Propagation Delay Measurement’: function not supported
Refined description of mode register evaluation timing
Removed description OPMODE.MODE1,0: no settings possible
SAI-evaluation / UOA-control:
- M4RMASK.bit6: only SAI-reporting via MON-2 is selected
- M4WMASK.bit6: in addition to UOA-bit control, also SAI-evaluation by the
state machine is selected; refined description
(see also
Figure 21
and
Figure 22)
Changed TEST.bit6 = ’1’ (not ’0’)
Statemachine is put into transparent state by TRANS=’0’ (not ’1’)
Refined reset timing description; added 900µs internal delay to figure
Refined description of FSC / Superframe-FSC-timing
Table 21:
Max. connection resistance specified
Removed input capacitance of pin XIN (pin XIN is not supported)
Page 129
Page 130
Page 135
Page 136
Page 137
Page 139
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PEF 24911
Table of Contents
1
1.1
1.2
1.3
1.4
2
2.1
2.2
2.3
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.3
3.4
3.5
3.6
3.7
3.8
3.8.1
3.8.2
3.8.3
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.16.1
3.16.2
3.16.3
4
4.1
4.2
4.3
Data Sheet
Page
1
2
4
5
9
11
11
12
19
20
20
21
22
23
24
24
28
30
33
34
34
34
36
41
43
45
46
47
50
52
53
54
55
57
58
62
64
69
69
69
71
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinning Changes from DFE-Q V1.3 to DFE-Q V2.1 . . . . . . . . . . . . . . . . .
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM®-2 Interface Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Superframe Marker Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM®-2 Command/ Indicate Channel . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM®-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MON-12 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface to the Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
U-Transceiver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2B1Q Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M4 Bit Reporting to State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M4, M5, M6 Bit Control Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start of Maintenance Bit Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Operations Channel (EOC) . . . . . . . . . . . . . . . . . . . . . . . . . . .
EOC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scrambling/ Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Encoding/ Decoding (2B1Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C/I Codes (2B1Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Machine Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LT Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inputs to the U-Transceiver in LT-Mode . . . . . . . . . . . . . . . . . . . . . . . .
Outputs of the U-Transceiver in LT-Mode . . . . . . . . . . . . . . . . . . . . . . .
LT-States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layer 1 Activation/ Deactivation Procedures . . . . . . . . . . . . . . . . . . . . . . .
2001-07-16
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