BF1005S...
Silicon N-Channel MOSFET Tetrode
•
For low noise, high gain controlled
input stages up to 1 GHz
•
Operating voltage 5 V
•
Integrated biasing network
•
Pb-free (RoHS compliant) package
1)
•
Qualified according AEC Q101
Drain
AGC
RF
Input
G2
G1
RF Output
+ DC
GND
ESD
(Electrostatic
discharge)
sensitive device, observe handling precaution!
Type
BF1005S
BF1005SR
Package
SOT143
SOT143R
1=S
1=D
2=D
2=S
Pin Configuration
3=G2
3=G1
4=G1
4=G2
-
-
-
-
Marking
NZs
NZs
Maximum Ratings
Parameter
Drain-source voltage
Continuous drain current
Gate 1/ gate 2-source current
Gate 1 (external biasing)
Total power dissipation
T
S
≤
76 °C
Storage temperature
Channel temperature
1
Pb-containing
Symbol
V
DS
I
D
±I
G1/2SM
+V
G1SE
P
tot
T
stg
T
ch
Value
8
25
10
3
200
-55 ... 150
150
Unit
V
mA
V
mW
°C
package may be available upon special request
Note:
It is not recommended to apply external DC-voltage on Gate 1 in active mode.
1
2007-04-20
BF1005S...
Thermal Resistance
Parameter
Channel - soldering point
1)
Symbol
R
thchs
Value
≤
370
Unit
K/W
Electrical Characteristics
at
T
A
= 25°C, unless otherwise specified
Parameter
Symbol
Values
min.
DC Characteristics
Drain-source breakdown voltage
I
D
= 650 µA,
V
G1S
= 0 ,
V
G2S
= 0
V
(BR)DS
Unit
max.
-
12
13
-
50
800
16
-
µA
nA
µA
mA
V
V
typ.
-
-
-
100
-
-
13
1
12
8
8
-
-
-
8
-
Gate1-source breakdown voltage
+
I
G1S
= 10 mA,
V
G2S
= 0 ,
V
DS
= 0
Gate2 source breakdown voltage
±
I
G2S
= 10 mA,
V
G1S
= 0 ,
V
DS
= 0
Gate1-source leakage current
V
G1S
= 6 V,
V
G2S
= 0
+
V
(BR)G1SS
±
V
(BR)G2SS
+
I
G1SS
±
I
G2SS
I
DSS
I
DSO
V
G2S(p)
Gate 2 source leakage current
±
V
G2S
= 8 V,
V
G1S
= 0 ,
V
DS
= 0
Drain current
V
DS
= 5 V,
V
G1S
= 0 ,
V
G2S
= 4 V
Operating current (selfbiased)
V
DS
= 5 V,
V
G2S
= 4 V
Gate2-source pinch-off voltage
V
DS
= 5 V,
I
D
= 100 µA
1
For
calculation of
R
thJA please refer to Application Note Thermal Resistance
2
2007-04-20
BF1005S...
Electrical Characteristics
at
T
A
= 25°C, unless otherwise specified
Parameter
Symbol
Values
min.
AC Characteristics
V
DS
= 5 V,
V
G2S
= 4.5 V
Gate1 input capacitance
V
DS
= 5 V,
V
G2S
= 4 V,
f
= 1 MHz
Output capacitance
V
DS
= 5 V,
V
G2S
= 4 V,
f
= 100 MHz
Power gain (self biased)
V
DS
= 5 V,
V
G2S
= 4 V,
f
= 800 MHz
Noise figure
V
DS
= 5 V,
V
G2S
= 4 V,
f
= 800 MHz
Gain control range
V
DS
= 5 V,
V
G2S
= 4 V ... 0 V,
f
= 800 MHz
∆G
p
40
50
-
F
-
1.6
2.1
dB
G
p
20
22
-
dB
C
dss
-
1.3
-
C
g1ss
-
2.4
2.7
pF
(verified by random sampling)
g
fs
26
30
-
mS
Forward transconductance
typ.
max.
Unit
3
2007-04-20
BF1005S...
Total power dissipation
P
tot
=
ƒ(T
S
)
BF1005S, BF1005SR
Total power dissipation
P
tot
=
ƒ(T
S
)
BF1005SW
220
mW
220
mA
180
160
180
160
P
tot
140
120
100
80
60
40
20
0
0
15
30
45
60
75
90 105 120
°C
150
P
tot
140
120
100
80
60
40
20
0
0
15
30
45
60
75
90 105 120
°C
150
T
S
T
S
Drain current
I
D
=
ƒ(V
G2S
)
Insertion power gain
|S
21
|² =
ƒ(V
G2S
)
20
mA
15
dB
16
-5
|S
21
|²
V
14
I
D
12
10
8
6
-15
-25
-35
-45
4
2
0
0
-55
0.5
1
1.5
2
2.5
3
3.5
4.5
-65
0
0.5
1
1.5
2
2.5
3
3.5
V
4.5
V
G2S
V
G2S
4
2007-04-20
BF1005S...
Forward transfer admittance
|Y
21
| =
ƒ(V
G2S
)
40
mS
pF
Gate 1 input capacitance
C
g1ss
=
ƒ(V
g2s
)
f = 200MHz
3
32
|Y
21
|
28
24
20
16
C
g1ss
V
2
1.5
1
12
8
0.5
4
0
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4.5
0.5
1
1.5
2
2.5
3
3.5
V
4.5
V
G2S
V
G2S
Output capacitance
C
dss
=
ƒ(V
G2S
)
f
= 200MHz
3
pF
C
dss
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
V
4.5
V
G2S
5
2007-04-20
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