SiT8924
Automotive AEC-Q100 Oscillator
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
AEC-Q100 with extended temperature range (-55°C to 125°C)
Frequencies between 1 MHz and 110 MHz accurate to 6 decimal
places
Supply voltage of 1.8V or 2.25V to 3.63V
Excellent total frequency stability as low as ±25 ppm
Industry best G-sensitivity of 0.1 PPB/G
Low power consumption of 3.8 mA typical at 1.8V
LVCMOS/LVTTL compatible output
Industry-standard packages: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2,
7.0 x 5.0 mm x mm
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
Automotive, extreme temperature and other high-rel electronics
Infotainment systems, collision detection devices, and in-vehicle
networking
Power train control
Electrical Specifications
Table 1. Electrical Characteristics
[1, 2]
Parameters
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
1
-25
-30
-50
Operating Temperature Range
(ambient)
T_use
-40
-40
-55
Supply Voltage
Current Consumption
Vdd
Idd
1.62
2.25
–
–
Duty Cycle
Rise/Fall Time
Output High Voltage
DC
Tr, Tf
VOH
45
–
–
90%
Typ.
–
–
–
–
–
–
–
1.8
–
4.0
3.8
–
1.5
1.3
–
Max.
110
+25
+30
+50
+105
+125
+125
1.98
3.63
4.8
4.5
55
3
2.5
–
Unit
MHz
ppm
ppm
ppm
°C
°C
°C
V
V
mA
mA
%
ns
ns
Vdd
Condition
Refer to
Table 13 and Table 14
for a list supported frequencies
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Frequency Range
Frequency Stability and Aging
Operating Temperature Range
Extended Industrial, AEC-Q100 Grade 2
Automotive, AEC-Q100 Grade 1
Extended Temperature, AEC-Q100
All voltages between 2.25V and 3.63V including 2.5V, 2.8V, 3.0V
and 3.3V are supported.
No load condition, f = 20 MHz, Vdd = 2.25V to 3.63V
No load condition, f = 20 MHz, Vdd = 1.8V
All Vdds
Vdd = 2.25V - 3.63V, 20% - 80%
Vdd = 1.8V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Pin 1, OE
Pin 1, OE
Pin 1, OE logic high or logic low
Measured from the time Vdd reaches 90% of final value
f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles
f = 75 MHz, 2.25V to 3.63V
f = 75 MHz, 1.8V
f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz
Supply Voltage and Current Consumption
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Input Characteristics
Input High Voltage
Input Low Voltage
Input Pull-up Impedence
Startup Time
Enable/Disable Time
RMS Period Jitter
RMS Phase Jitter (random)
VIH
VIL
Z_in
T_start
T_oe
T_jitt
T_phj
70%
–
–
–
–
–
–
–
–
–
–
100
–
–
1.6
1.9
0.5
1.3
–
30%
–
10
130
Jitter
2.5
3.0
–
–
ps
ps
ps
ps
Vdd
Vdd
k
ms
ns
Startup and Resume Timing
Notes:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and
at 25 °C temperature.
SiTime Corporation
Rev. 1.01
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised June 18, 2015
SiT8924
Automotive AEC-Q100 Oscillator
The Smart Timing Choice
The Smart Timing Choice
Table 2. Pin Description
Pin
1
2
3
4
Symbol
Output Enable
OE/NC
No Connect
GND
OUT
VDD
Power
Output
Power
H
[3]
:
Functionality
specified frequency output
L: output is high impedance. Only output driver is disabled.
Any voltage between 0 and Vdd or Open
[3]
: Specified frequency
output. Pin 1 has no function.
Electrical ground
[4]
Oscillator output
Power supply voltage
[4]
GND
2
Top View
OE/NC
1
4
VDD
3
OUT
Notes:
3. In OE mode, a pull-up resistor of 10k or less is recommended if pin 1 is not externally driven.
If pin 1 needs to be left floating, use the NC option.
4. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
N
Figure 1. Pin Assignments
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the
IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
[5]
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Note:
5.Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration
[6]
Package
7050
5032
3225
2520
2016
JA, 4 Layer Board
(°C/W)
142
97
109
117
152
JA, 2 Layer Board
(°C/W)
273
199
212
222
252
JC, Bottom
(°C/W)
30
24
27
26
36
Note:
6. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
Table 5. Maximum Operating Junction Temperature
[7]
Max Operating Temperature (ambient)
105°C
125°C
Maximum Operating Junction Temperature
115°C
135°C
Note:
7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.01
Page 2 of 12
www.sitime.com
SiT8924
Automotive AEC-Q100 Oscillator
The Smart Timing Choice
The Smart Timing Choice
Test Circuit and Waveform
[8]
Vdd
Vout
Test
Point
tr
80% Vdd
tf
4
Power
Supply
0.1µF
3
15pF
(including probe
and fixture
capacitance)
50%
20% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
1
2
Vdd
OE/NC Function
1k
Figure 2. Test Circuit
Note:
8. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 3. Waveform
Timing Diagrams
u
90% Vdd
Vdd
Vdd
50% Vdd
Pin 4 Voltage
T_start
No Glitch
during start up
[9]
OE Voltage
T_oe
CLK Output
HZ
CLK Output
HZ
T_start: Time to start from power-off
T_oe: Time to re-enable the clock output
Figure 4. Startup Timing (OE Mode)
Vdd
OE Voltage
50% Vdd
Figure 5. OE Enable Timing (OE Mode Only)
T_oe
CLK Output
HZ
T_oe: Time to put the output in High Z mode
Figure 6. OE Disable Timing (OE Mode Only)
Note:
9 SiT8924 has “no runt” pulses and “no glitch” output during startup or resume.
Rev. 1.01
Page 3 of 12
www.sitime.com
FPGA/CPLD
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