Serial Configuration (EPCS) Devices
Datasheet
C51014-5.1
Datasheet
This datasheet describes serial configuration (EPCS) devices.
Supported Devices
Table 1
lists the supported Altera
EPCS devices.
Table 1. Altera EPCS Devices
Device
EPCS1
EPCS4
EPCS16
EPCS64
EPCS128
Memory Size
(bits)
1,048,576
4,194,304
16,777,216
67,108,864
134,217,728
On-Chip
Decompression
Support
No
No
No
No
No
ISP Support
Yes
Yes
Yes
Yes
Yes
Cascading
Support
No
No
No
No
No
Reprogrammable
Yes
Yes
Yes
Yes
Yes
Recommended
Operating
Voltage (V)
3.3
3.3
3.3
3.3
3.3
f
For more information about programming EPCS devices using the Altera
Programming Unit (APU) or Master Programming Unit (MPU), refer to the
Altera
Programming Hardware Datasheet.
f
The EPCS device can be re-programmed in system with ByteBlaster
II download
cable or an external microprocessor using SRunner. For more information, refer to
AN418: SRunner: An Embedded Solution for Serial Configuration Device Programming.
Features
EPCS devices offer the following features:
■
■
■
■
■
■
Supports active serial (AS) x1 configuration scheme
Easy-to-use four-pin interface
Low cost, low pin count, and non-volatile memory
Low current during configuration and near-zero standby mode current
2.7-V to 3.6-V operation
EPCS1, EPCS4, and EPCS16 devices available in 8-pin small-outline integrated
circuit (SOIC) package
EPCS64 and EPCS128 devices available in 16-pin SOIC package
■
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San Jose, CA 95134
www.altera.com
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April 2014
Altera Corporation
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Functional Description
■
Enables the Nios
processor to access unused flash memory through AS memory
interface
Reprogrammable memory with more than 100,000 erase or program cycles
Write protection support for memory sectors using status register bits
In-system programming (ISP) support with SRunner software driver
ISP support with USB-Blaster
, EthernetBlaster, or ByteBlaster II download cables
Additional programming support with the APU and programming hardware
from BP Microsystems, System General, and other vendors
By default, the memory array is erased and the bits are set to
1
■
■
■
■
■
■
Functional Description
To configure a system using an SRAM-based device, each time you power on the
device, you must load the configuration data. The EPCS device is a flash memory
device that can store configuration data that you use for FPGA configuration purpose
after power on. You can use the EPCS device on all FPGA that support AS x1
configuration scheme.
For an 8-pin SOIC package, you can migrate vertically from the EPCS1 device to the
EPCS4 or EPCS16 device. For a 16-pin SOIC package, you can migrate vertically from
the EPCS64 device to the EPCS128 device.
With the new data decompression feature supported, you can determine using which
EPCS device to store the configuration data for configuring your FPGA.
Example 1
shows how you can calculate the compression ratio to determine which
EPCS device is suitable for the FPGA.
Example 1. Compression Ratio Calculation
EP4SGX530 = 189,000,000 bits
EPCS128 = 134,217,728 bits
Preliminary data indicates that compression typically reduces the
configuration bitstream size by 35% to 55%. Assume worst case that is 35%
decompression.
189,000,000 bits x 0.65 = 122,850,000 bits
The EPCS128 device is suitable.
f
For more information about the FPGA decompression feature, refer to the
configuration chapter in the appropriate device handbook.
Serial Configuration (EPCS) Devices Datasheet
April 2014
Altera Corporation
Active Serial FPGA Configuration
Page 3
Figure 1
shows the EPCS device block diagram.
Figure 1. EPCS Device Block Diagram
EPCS Device
nCS
DCLK
Control
Logic
DATA
I/O Shift
Register
ASDI
Address Counter
Data Buffer
Status Register
Decode Logic
Memory
Array
Accessing Memory in EPCS Devices
You can access the unused memory locations of the EPCS device to store or retrieve
data through the Nios processor and SOPC Builder. SOPC Builder is an Altera tool for
creating bus-based (especially microprocessor-based) systems in Altera devices.
SOPC Builder assembles library components such as processors and memories into
custom microprocessor systems.
SOPC Builder includes the EPCS device controller core, which is an interface core
designed specifically to work with the EPCS device. With this core, you can create a
system with a Nios embedded processor that allows software access to any memory
location within the EPCS device.
Active Serial FPGA Configuration
The following Altera FPGAs support the AS configuration scheme with EPCS devices:
■
■
■
Arria
series
Cyclone
series
All device families in the Stratix
series except the Stratix device family
There are four signals on the EPCS device that interface directly with the FPGA’s
control signals. The EPCS device signals are
DATA, DCLK, ASDI,
and
nCS
interface with
the
DATA0, DCLK, ASDO,
and
nCSO
control signals on the FPGA, respectively.
1
For more information about the EPCS device pin description, refer to
Table 23 on
page 36.
April 2014
Altera Corporation
Serial Configuration (EPCS) Devices Datasheet
Page 4
Active Serial FPGA Configuration
Figure 2
shows the configuration of an FPGA device in the AS configuration scheme
with an EPCS device using a download cable.
Figure 2. Altera FPGA Configuration in AS Mode Using a Download Cable
V
CC
(1)
10 kΩ
V
CC
(1)
V
CC
(1)
10 kΩ
Altera FPGA
CONF_DONE
nSTATUS
nCONFIG
EPCS Device
(2)
nCE
10 kΩ
DATA
DCLK
nCS
ASDI
DATA0
DCLK
nCSO
ASDO
MSEL[]
(3)
nCEO
N.C.
(1), (4)
10 kΩ
Pin 1
V
CC
(1)
Notes to
Figure 2:
(1) For more information about the V
CC
value, refer to the configuration chapter in the appropriate device handbook.
(2) EPCS devices cannot be cascaded.
(3) Connect the
MSEL[]
input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate
device handbook.
(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration
chapter in the appropriate device handbook.
Serial Configuration (EPCS) Devices Datasheet
April 2014
Altera Corporation
Active Serial FPGA Configuration
Page 5
Figure 3
shows the configuration of an FPGA device in the AS configuration scheme
with an EPCS device using the APU or a third-party programmer.
Figure 3. Altera FPGA Configuration in AS Mode Using APU or a Third-party Programmer
(1),
V
CC
(1)
10 kΩ
V
CC
(1)
V
CC
(1)
10 kΩ
Altera FPGA
CONF_DONE
nSTATUS
nCONFIG
EPCS Device
(2)
nCE
MSEL[]
(3)
nCEO
N.C.
(4)
10 kΩ
DATA
DCLK
nCS
ASDI
DATA0
DCLK
nCSO
ASDO
Notes to
Figure 3:
(1) For more information about the V
CC
value, refer to the configuration chapter in the appropriate device handbook.
(2) EPCS devices cannot be cascaded.
(3) Connect the
MSEL[]
input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate
device handbook.
(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration
chapter in the appropriate device handbook.
In an AS configuration, the FPGA acts as the configuration master in the
configuration flow and provides the clock to the EPCS device. The FPGA enables the
EPCS device by pulling the
nCS
signal low using the
nCSO
signal as shown in
Figure 2
and
Figure 3.
Then, the FPGA sends the instructions and addresses to the EPCS device
using the
ASDO
signal. The EPCS device responds to the instructions by sending the
configuration data to the FPGA’s
DATA0
pin on the falling edge of
DCLK.
The data is
latched into the FPGA on the next
DCLK
signal’s falling edge.
1
Before the FPGA enters configuration mode, ensure that V
CC
of the EPCS device is
ready. If V
CC
is not ready, you must hold
nCONFIG
low until all power rails of EPCS
device are ready.
The FPGA controls the
nSTATUS
and
CONF_DONE
pins during configuration in the AS
mode. If the
CONF_DONE
signal does not go high at the end of configuration, or if the
signal goes high too early, the FPGA pulses its
nSTATUS
pin low to start a
reconfiguration. If the configuration is successful, the FPGA releases the
CONF_DONE
pin, allowing the external 10-k resistor to pull the
CONF_DONE
signal high. The FPGA
initialization begins after the
CONF_DONE
pin goes high. After the initialization, the
FPGA enters user mode.
f
For more information about configuring the FPGAs in AS configuration mode or
other configuration modes, refer to the configuration chapter in the appropriate
device handbook.
April 2014
Altera Corporation
Serial Configuration (EPCS) Devices Datasheet
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