DEMO MANUAL DC1525A
LTC2175-14/-12,
LTC2174-14/-12, LTC2173-14/-12, LTC2172-14/-12,
LTC2171-14/-12, LTC2170-14/-12
12-Bit/14-Bit, 25Msps to 125Msps Quad ADCs
DESCRIPTION
Demonstration circuit 1525A supports a family of
14-Bit/12-Bit 25Msps to 125Msps ADCs. Each assem-
bly features one of the following devices: LTC
®
2175-14,
LTC2175-12, LTC2174-14, LTC2174-12, LTC2173-14,
LTC2173-12, LTC2172-14, LTC2172-12, LTC2171-14,
LTC2171-12, LTC2170-14, LTC2170-12 high speed,
quad ADCs.
The versions of the 1525A demo board are listed in Table 1.
Depending on the required resolution and sample rate,
Table 1. DC1525A Variants
DC1525A VARIANTS
1525A-A
1525A-B
1525A-C
1525A-D
1525A-E
1525A-F
1525A-G
1525A-H
1525A-I
1525A-J
1525A-K
1525A-L
ADC PART NUMBER
LTC2175-14
LTC2174-14
LTC2173-14
LTC2172-14
LTC2171-14
LTC2170-14
LTC2175-12
LTC2174-12
LTC2173-12
LTC2172-12
LTC2171-12
LTC2170-12
RESOLUTION
14-Bit
14-Bit
14-Bit
14-Bit
14-Bit
14-Bit
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
MAXIMUM SAMPLE RATE
125Msps
105Msps
80Msps
65Msps
40Msps
25Msps
125Msps
105Msps
80Msps
65Msps
40Msps
25Msps
INPUT FREQUENCY
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
the DC1525A is supplied with the appropriate ADC. The
circuitry on the analog inputs is optimized for analog input
frequencies from 5MHz to 140MHz. Refer to the data sheet
for proper input networks for different input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, μModule, Linear Technology and the Linear logo are registered trademarks
and QuikEval and PScope are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
dc1525af
1
DEMO MANUAL DC1525A
PERFORMANCE SUMMARY
PARAMETER
Supply Voltage: DC1525A
Analog Input Range
Logic Input Voltages
Logic Output Voltages (Differential)
Sampling Frequency (Convert Clock Frequency)
Encode Clock Level
Encode Clock Level
Resolution
Input Frequency Range
SFDR
SNR
(T
A
= 25°C)
VALUE
Optimized for 3V
[3V
↔
6.0V Min/Max]
1V
P-P
to 2V
P-P
1.3V
0.6V
350mV/1.25V Common Mode
247mV/1.25V Common Mode
0V to 3.6V
0.2V to 3.6V
CONDITION
Depending on Sampling Rate and the A/D Converter Provided,
this Supply Must Provide Up to 500mA.
Depending on SENSE Pin Voltage
Minimum Logic High
Maximum Logic Low
Nominal Logic Levels (100Ω Load, 3.5mA Mode)
Minimum Logic Levels (100Ω Load, 3.5mA Mode)
See Table 1
Single-ended Encode Mode (ENC
–
Tied to GND)
Differential Encode Mode (ENC
–
Not Tied to GND)
See Table 1
See Table 1
See Applicable Data Sheet
See Applicable Data Sheet
QUICK START PROCEDURE
Demonstration circuit 1525A is easy to set up to evaluate
the performance of the LTC2175 A/D converters. Refer to
Figure 1 for proper measurement equipment setup and
follow this procedure.
Setup
If a DC1371 QuikEval™ II Data Acquisition and Collection
System was supplied with the DC1525A demonstration
circuit, follow the DC1371 Quick Start Guide to install the
required software and for connecting the DC1371 to the
DC1525A and to a PC.
DC1525A Demonstration Circuit Board Jumpers
The DC1525A demonstration circuit board should have
the following jumper settings as default positions: (as
per Figure 1).
J13: PAR/SER: Selects Parallel or Serial programming
mode. (Default – Serial)
Optional Jumpers:
J8: Term: Enables/Disable optional output termination.
(Default – Removed)
J5: ILVDS: Selects either 1.75mA or 3.5mA of output
current for the LVDS drivers. (Default – Removed)
J14: LANE: Selects either 1 lane or 2 lane output modes
(Default – Removed) NOTE: The DC1371 does not support
1 lane operation.
J15: SHDN: Enables and disables the LTC2175. (De-
fault – Removed)
J2: WP: Enable/Disables write protect for the EEPROM.
(Default – Removed)
Note: optional jumper should be left open to ensure proper
serial configuration.
Applying Power and Signals to the DC1525A
Demonstration Circuit
The DC1371 is used to acquire data from the DC1525A,
the DC1371 must FIRST be connected to a powered USB
port and have equal to 5V applied power BEFORE applying
3.6V to 6V across the pins marked V
+
and GND on the
DC1525A. DC1525A requires 3.6V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1525A demonstration circuit requires up
to 500mA depending on the sampling rate and the A/D
converter supplied.
The DC1525A should not be removed, or connected to
the DC1371 while power is applied.
dc1525af
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DEMO MANUAL DC1525A
QUICK START PROCEDURE
3.5V
TO 6V
ANALOG INPUTS
CHANNEL 1
TO PROVIDED
POWER SUPPLY
CHANNEL 2
USE PROVIDED
USB CABLE
PARALLEL/SERIAL
CHANNEL 3
CHANNEL 4
dc1525a F01
SINGLE-ENDED ENCODE CLOCK
USE PROVIDED DC1075
Figure 1. DC1525A Setup
Analog Input Network
For optimal distortion and noise performance the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen-
cies above 140MHz, refer to the LTC2175 data sheet for a
proper input network. Other input networks may be more
appropriate for input frequencies less that 5MHz.
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide Gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Apply the analog input signal of interest to the SMA con-
nectors on the DC1525A demonstration circuit board
marked J3 AIN1, J4 AIN2, J6 AIN3, J7 AIN4. These inputs
correspond with channels 1 to 4 of the ADC respectively.
These inputs are capacitive coupled to Balun transform-
ers ETC1-1-13.
Encode Clock
NOTE: Apply an encode clock to the SMA connector on
the DC1525A demonstration circuit board marked J11
CLK+. As a default the DC1525A is populated to have a
single-ended input.
For the best noise performance, the ENCODE INPUT must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
P-P
or 13dBm. When
dc1525af
3
DEMO MANUAL DC1525A
QUICK START PROCEDURE
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075A that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2175.
Using bandpass filters on the clock and the analog input
will improve the noise performance by reducing the
wideband noise power of the signals. In the case of the
DC1525A a bandpass filter used for the clock should be
used prior to the DC1075A. Data sheet FFT plots are taken
with 10 pole LC filters made by TTE (Los Angeles, CA) to
suppress signal generator harmonics, non-harmonically
related spurs and broadband noise. Low phase noise Agi-
lent 8644B generators are used for both the Clock input
and the Analog input.
Digital Outputs
Data outputs, data clock, and frame clock signals are avail-
able on J1 of the DC1525A. This connector follows the
VITA-57/FMC standard, but all signals should be verified
when using an FMC carrier card other than the DC1371.
Software
The DC1371 is controlled by the PScope™ System Soft-
ware provided or downloaded from the Linear Technology
website at http://www.linear.com/software/.
To start the data collection software if PScope.exe is in-
stalled (by default) in \Program Files\LTC\PScope\, double
click the PScope Icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC1525A demonstration circuit is properly connected
to the DC1371, PScope should automatically detect the
DC1525A, and configure itself accordingly.
If everything is hooked up properly, powered and a suit-
able convert clock is present, clicking the Collect button
should result in time and frequency plots displayed in
the PScope window. Additional information and help for
Figure 4. Demobd Configuration Options
Figure 3. PScope Toolbar
PScope is available in the DC1371 Quick Start Guide and in
the online help available within the PScope program itself.
Serial Programming
PScope has the ability to program the DC1525A board
serially through the DC1371. There are several options
available in the LTC2175 family that are only available
through serially programming. PScope allows all of these
features to be tested.
These options are available by first clicking on the Set
Demo Bd Options icon on the PScope toolbar (Figure 3).
This will bring up the menu shown in Figure 4.
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DEMO MANUAL DC1525A
QUICK START PROCEDURE
This menu allows any of the options available for the
LTC2175 family to be programmed serially. The LTC2175
family has the following options:
Randomizer: Enables Data Output Randomizer
• Off (Default): Disables data output randomizer
• On: Enables data output randomizer
Two’s Complement: Enables two’s complement mode
• Off (Default): Selects offset binary mode
• On: Selects two’s complement mode
Sleep Mode: Selects between normal operation, sleep
mode:
• Off (Default): Entire ADC is powered, and active
• On: The entire ADC is powered down.
Channel 1 Nap: Selects between normal operation and
putting channel 1 in nap mode.
• Off (Default): Channel one is active
• On: Channel one is in nap mode
Channel 2 Nap: Selects between normal operation and
putting channel 2 in nap mode.
• Off (Default): Channel two is active
• On: Channel two is in nap mode
Channel 3 Nap: Selects between normal operation and
putting channel 3 in nap mode.
• Off (Default): Channel three is active
• On: Channel three is in nap mode
Channel 4 Nap: Selects between normal operation and
putting channel 4 in nap mode.
• Off (Default): Channel four is active
• On: Channel four is in nap mode
Output Current: Selects the LVDS output drive current
• 1.75mA (Default): LVDS output driver current
• 2.1mA: LVDS output driver current
• 2.5mA: LVDS output driver current
• 3.0mA: LVDS output driver current
• 3.5mA: LVDS output driver current
• 4.0mA: LVDS output driver current
• 4.5mA: LVDS output driver current
Internal Termination: Enables LVDS internal termination
• Off (Default): Disables internal termination
• On: Enables internal termination
Outputs: Enables Digital Outputs
• Enabled (Default): Enables digital outputs
• Disabled: Disables digital outputs
Test Pattern: Selects Digital output test patterns. The
desired test pattern can be entered into the text boxes
provided.
• Off(default): ADC input data is displayed
• On: Test pattern is displayed.
Once the desired settings are selected hit OK and PScope
will automatically update the register of the device on the
DC1525A demo board.
dc1525af
5
FPGA/CPLD
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