9.0 8051 Special Function Registers .................................................................................................................................................. 27
11.0 USB Controller Description ......................................................................................................................................................... 92
12.0 GPIO and LED Interface ........................................................................................................................................................... 117
13.0 Two Pin Serial Port (UART) ...................................................................................................................................................... 132
14.0 Serial Peripheral Interconnect (SPI1) - Master ......................................................................................................................... 145
15.0 Clock and Reset ........................................................................................................................................................................ 150
16.0 OTP ROM Test Interface .......................................................................................................................................................... 176
17.0 TEST Modes, JTAG, and XNOR .............................................................................................................................................. 187
18.0 DC Parameters ......................................................................................................................................................................... 188
Appendix C: Revision History ........................................................................................................................................................... 213
The Microchip Web Site .................................................................................................................................................................... 214
Customer Change Notification Service ............................................................................................................................................. 214
Customer Support ............................................................................................................................................................................. 214
Product Identification System ........................................................................................................................................................... 215
2013 - 2016 Microchip Technology Inc.
DS00001561C-page 3
SEC1110/SEC1210
1.0
INTRODUCTION
The SEC1110 and SEC1210 provide a single-chip solution for a Smart Card bridge to USB and UART interfaces. These
bridges are controlled by an enhanced 8051 micro controller and all chip peripherals are accessed and controlled
through the SFR or XDATA register space.
1.1
Features
• Smart Card
- Fully compliant with standards: ISO/IEC 7816, EMV 4.2/4.3, ETSI TS 102 221 and PC/SC
- Versatile ETU rate generation, supporting current and proposed rates (to 826 Kbps and beyond)
- Full support of both T=0 and T=1 protocols
- Full-packet FIFO (261 bytes), for transmit and receive
- Half-duplex operation, with no software intervention required between Transmit and Receive phases of an
exchange
- Very loose real-time response required of software: approximately 180 ms worst case
- Dynamically programmable FIFO threshold, with byte granularity
- Time-out FIFO flush interrupt, independent of threshold
- Programmable Smart Card clock frequency
- UART-like register file structure
- Supports Class A, Class B, Class C, or Class AB Smart Cards (all 1.8 V, 3.0 V and 5.0 V cards)
- Automatic character repetition for T=0 protocol parity error recovery
- Automatic card deactivation on card removal and on other system events, including persistent parity errors
- Internal procedure byte filtering for T=0 protocol
- Protocol timers (guard, time-out and CWT) for EMV-defined timing parameters
-
-
-
-
-
Detection of an unresponsive card
Activation/deactivation sequences
Cold/warm resets
Monitoring for all EMV timing constraints
16-bit general purpose down counter for software timing use
- Fully compliant ESD protection on card pins per JESD22-A114D (March 2006) and JESD22-A115A “Machine
Model” from AN1181
- Fully EMV compliant, internal signal current limits
- 3.3 V internal operation with 5.0 V tolerant buffers where required
- Self-contained management of Smart Card power:
-
-
-
-
-
SC1_VCC and SC2_VCC, supply output
Regulator for 1.8 V, 3.0 V, and 5.0 V from supply input
Current limiter with over-current sense interrupt (short circuit detect)
Hardware-ensured, compliant deactivation sequence on card removal
Synchronous card support
• USB
- 12 Mbps USB operation compliant with the
USB 2.0 Specification
- Integrated USB 1.5 K pull-up resistor
- Integrated Series resistors on USB_DP, USB_DM
- Integrated USB devices controller with:
- 8/16/32/64 byte control endpoint 0 buffer
- Five 8/16/32/64 byte programmable (bulk/interrupt) endpoint buffers
• 8051
- Reduced instruction cycle time (approximately 9 times 80C51)
- 9.6 MHz max clock speed
- Enhanced peripherals: two 16-bit timers, watch dog timer, interrupt controller, JTAG
- 16 KB One Time Programmable (OTP) ROM
- 1.5 KB RAM
- 4 KB (SEC1100/SEC1200)/ 16KB (SEC1110/SEC1210) ROM
DS00001561C-page 4
2013 - 2016 Microchip Technology Inc.
SEC1110/SEC1210
• UART
- Standard PC (9600, 19200, 38400 and 115200) baud rates supported
- 3 M baud high-speed rate (non-PC standard)
• SPI
- Master capability with 12 MHz max performance
• General
- 5.0 V tolerance on user accessible IO pins
- Self-clocking internal oscillator, no external crystal required
- 3.6 V-5.5 V supply input
- Internal 4.8 V comparator disables Class A card support if the input voltage is too low
1.2
Smart Card Subsystem
The SEC1110 and SEC1210 are fully compliant with the prevailing Smart Card standards: ISO7816, EMV, and PC/SC.
It meets and exceeds all existing requirements for communication bit rate (ETU duration) and includes support for pro-
posed bit rates up to 826 Kbps. Signal levels and current limits are also fully compliant.
The Smart Card power is regulated and switched internally, supporting all 5.0 V, 3.0 V, and 1.8 V Smart Cards (classes
A, B, and C, respectively). Over-current protection is provided, and a detected over-current condition is available as an
interrupt. The required standard activation and deactivation sequences are provided with software interaction. However,
deactivation is handled in hardware as the card is being removed. This scenario ensures the required sequence regard-
less of software participation. If the system clock is inactive at the time, the card movement is detected asynchronously,
and the Wake-On Event feature is used to re-start the system clock so that the de-activation sequence can continue.
Interface signals to the Smart Card are designed to meet both standard drive levels and current limitations internally,
requiring no external series resistors. ESD protection on these signals meets the full standard requirements.
The device is a superset of the familiar 16450 UART architecture, with extensions in the form of a larger FIFO, special-
ized state machines for T=0 protocol parsing, automatic half-duplex turnaround at the completion of a transmitted mes-
sage, and a specially-designed set of timers to enforce standards compliance in timing (as required of a terminal by the
ISO7816 and EMV standards).
With the full-packet-depth FIFO on-chip, software is almost totally excluded from real-time requirements. It loads an out-
going message into the FIFO, triggers the transfer, and reads the returned data at any time after it becomes available.
The reset sequence (cold or warm) is equally hands-off: software sets up the sequence and activates the reset, and is
alerted when the ATR message has been received (via the FIFO Threshold Interrupt). The threshold is dynamically pro-
grammable with byte granularity, so that threshold interrupts can be received at various stages in the processing of a
message of initially unknown length (such as ATR).
For detecting data time-outs, and for other mandatory timing tasks having to do with communication with a Smart Card,
a set of three protocol timers is provided:
• Time-out timer, for monitoring the standard WWT, BWT and WTX time-out intervals
• CWT timer, for monitoring the T=1 CWT time-out interval
• Guard timer, for ensuring the BGT and EGT transmission intervals, with special usage during a Reset sequence.
A separate general purpose timer is provided for software driver use.
Synchronous card support using GPIOs controlled via registers in the Smart Card device.
FPGA/CPLD
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