bus buffer allows I/O card insertion into a live backplane
without corruption of the data and clock busses. In addi-
tion, the LTC4301 allows the V
CC
, SDAIN and SCLIN pull-
up voltage and the SDAOUT and SCLOUT pull-up voltage
to be independent from each other. Control circuitry
prevents the backplane from being connected to the card
until a stop bit or a bus idle is present. When the connec-
tion is made, the LTC4301 provides bidirectional buffer-
ing, keeping the backplane and card capacitances isolated.
During insertion, the SDA and SCL lines are precharged to
1V to minimize bus disturbances. When driven low, the CS
input pin allows the part to connect after a stop bit or bus
idle occurs. Driving CS high breaks the connection be-
tween SCLIN and SCLOUT and between SDAIN and
SDAOUT. The READY output pin indicates that the back-
plane and card sides are connected together.
The LTC4301 is offered in 8-pin DFN (3mm
×
3mm) and
MSOP packages.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 7032051.
APPLICATIO S
■
■
■
■
■
Hot Board Insertion
Servers
Capacitance Buffer/Bus Extender
Desktop Computers
CompactPCI
TM
and ATCA Systems
TYPICAL APPLICATIO
3.3V
5V
0.01µF
10k
10k
BACK_SCL
10k
V
CC
LTC4301
10k
STAGGERED CONNECTOR
SCLIN
SCLOUT
CARD_SCL
OUTPUT
SIDE
20pF
SDAIN
5V
10k
CS
GND
SDAOUT
CARD_SDA
BACK_SDA
1V/DIV
READY
4301
TA01
BACKPLANE
CONNECTOR
CARD
U
Input-Output Connection
INPUT
SIDE
55pF
4301 TA01b
U
U
1µs/DIV
4301fb
1
LTC4301
ABSOLUTE
MAXIMUM
RATINGS
V
CC
to GND ................................................. –0.3V to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT, CS ........ –0.3V to 7V
READY ........................................................ –0.3V to 6V
Operating Temperature Range
LTC4301C ............................................... 0°C to 70°C
LTC4301I ............................................ – 40°C to 85°C
PACKAGE/ORDER INFORMATION
TOP VIEW
CS 1
SCLOUT 2
SCLIN 3
GND 4
9
8
7
6
5
V
CC
SDAOUT
SDAIN
READY
ORDER PART
NUMBER
LTC4301CDD
LTC4301IDD
DD PART
MARKING*
LBBY
TOP VIEW
CS
SCLOUT
SCLIN
GND
1
2
3
4
8
7
6
5
V
CC
SDAOUT
SDAIN
READY
DD PACKAGE
8-LEAD (3mm
×
3mm) PLASTIC DFN
T
JMAX
= 125°C,
θ
JA
= 43°C/W
EXPOSED PAD (PIN 9)
PCB CONNECTION OPTIONAL
Order Options
Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL
Power Supply
V
CC
I
CC
Positive Supply Voltage
Supply Current
PARAMETER
The
●
indicates specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 2.7V to 5.5V, unless otherwise noted.
CONDITIONS
●
V
CC
= 5.5V, V
SDAIN
= V
SCLIN
= 0V
V
CC
= 5.5V, CS = 5.5V
SDA, SCL Floating
I
PULLUP
= 3mA
CS from 0V to V
CC
Rising Edge
(Note 3)
Start-Up Circuitry
V
PRE
t
IDLE
RDY
VOL
V
THRCS
I
CS
V
THR
V
HYS
t
PLH
t
PHL
I
OFF
Precharge Voltage
Bus Idle Time
READY Output Low Voltage
Connection Sense Threshold
CS Input Current
SDA, SCL Logic Input Threshold Voltage
SDA, SCL Logic Input Threshold Voltage
Hysteresis
CS Delay On-Off
READY Delay Off-On
CS Delay Off-On
READY Delay On-Off
Ready Off Leakage Current
●
●
●
2
U
U
W
W W
U
W
(Note 1)
Storage Temperature Range
MSOP ............................................... – 65°C to 150°C
DFN .................................................. – 65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC4301CMS8
LTC4301IMS8
MS8 PART
MARKING*
LTBBW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 200°C/W
MIN
2.7
TYP
MAX
5.5
UNITS
V
mA
µA
V
µs
V
V
µA
V
mV
ns
ns
µs
ns
µA
4301fb
●
4.5
300
0.85
60
0.8
1.55
1.05
95
1.4
±0.1
1.8
50
10
10
95
10
±0.1
6.2
1.25
175
0.4
2
±1
2.0
LTC4301
ELECTRICAL CHARACTERISTICS
SYMBOL
V
OS
C
IN
I
LEAK
V
OL
f
I2C,MAX
t
BUF
t
HD,STA
t
SU,STA
t
SU,STO
t
HD,DATI
t
SU,DAT
PARAMETER
Input-Output Offset Voltage
Digital Input Capacitance SDAIN, SDAOUT,
SCLIN, SCLOUT
Input Leakage Current
Output Low Voltage, Input = 0V
I
2
C Maximum Operating Frequency
Bus Free Time Between Stop and Start
Condition
Hold Time After (Repeated) Start Condition
Repeated Start Condition Set-Up Time
Stop Condition Set-Up Time
Data Hold Time Input
Data Set-Up Time
Input-Output Connection
The
●
indicates specifications which apply over the full operating
= 25°C. V
CC
= 2.7V to 5.5V, unless otherwise noted.
temperature range, otherwise specifications are at T
A
CONDITIONS
10k to V
CC
on SDA, SCL, V
CC
= 3.3V,
SDA or SCL = 0.2V (Note 2)
(Note 3)
SDA, SCL Pins
SDA, SCL Pins, I
SINK
= 3mA, V
CC
= 2.7V
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
●
●
MIN
0
TYP
100
MAX
175
10
±5
UNITS
mV
pF
µA
V
kHz
0
400
600
0.4
Timing Characteristics
1.3
100
0
0
0
100
µs
ns
ns
ns
ns
ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and V
CC
voltage is shown in the Typical Performance
Characteristics section.
Note 3:
Determined by design, not tested in production.
TYPICAL PERFOR A CE CHARACTERISTICS
I
CC
vs Temperature
4.9
4.8
4.7
4.6
I
CC
(mA)
V
CC
= 5.5V
80
4.4
4.3
4.2
4.1
4.0
V
CC
= 3.3V
V
CC
= 2.7V
TIME (ns)
4.5
60
V
OUT
– V
IN
(mV)
3.9
–80 –60 –40 –20 0 20 40 60
TEMPERATURE (°C)
U W
4301 G01
Input – Output High to Low
Propagation Delay vs Temperature
100
V
CC
= 2.7V
250
V
CC
= 3.3V
200
150
300
Connection Circuitry V
OUT
– V
IN
T
A
= 25°C
V
IN
= 0V
40
V
CC
= 5V
100
V
CC
= 3.3V
50
0
V
CC
= 5.5V
20
C
IN
= C
OUT
= 100pF
R
PULLUPIN
= R
PULLUPOUT
= 10k
–25
0
25
50
TEMPERATURE (°C)
75
100
4301 G02
80 100
0
–50
0
10,000
20,000
30,000
R
PULLUP
(Ω)
40,000
4301 G03
4301fb
3
LTC4301
PI FU CTIO S
CS (Pin 1):
The connection sense pin is a 1.4V threshold
digital input pin. For normal operation CS is grounded.
Driving CS above the 1.4V threshold isolates SDAIN from
SDAOUT and SCLIN from SCLOUT and asserts READY
low.
SCLOUT (Pin 2):
Serial Clock Output. Connect this pin to
the SCL bus on the card.
SCLIN (Pin 3):
Serial Clock Input. Connect this pin to SCL
on the bus backplane.
GND (Pin 4):
Ground. Connect this pin to a ground plane
for best results.
READY (Pin 5):
The READY pin is an open drain N-channel
MOSFET output which pulls down when CS is high or
when the start-up sequence described in the Operation
section has not been completed. READY goes high when
CS is low and a start-up is complete.
SDAIN (Pin 6):
Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SDAOUT (Pin 7):
Serial Data Output. Connect this pin to
the SDA bus on the card.
V
CC
(Pin 8):
Main Input Supply. Place a bypass capacitor
of at least 0.01µF close to V
CC
for best results.
Exposed Pad (Pin 9):
Exposed pad may be left open or
connected to device ground.
BLOCK DIAGRA
6
SDAIN
3
SCLIN
1.8V
1.8V
1
CS
95µs
DELAY
1.4V
4
W
U
U
U
LTC4301 Supply Independent 2-Wire Bus Buffer
PRECHARGE
V
CC
8
R1
200k
PRECHARGE
R2
CONNECT
200k
CONNECT PRECHARGE
CONNECT
R3
200k
R4
200k
SDAOUT
7
CONNECT
SCLOUT
2
LOGIC
PRECHARGE
CONNECT
CONNECT
READY
5
UVLO
CONNECT
GND
4
4301 BD
4301fb
LTC4301
OPERATIO
Start-Up
When the LTC4301 first receives power on its V
CC
pin,
either during power-up or live insertion, it starts in an
undervoltage lockout (UVLO) state, ignoring any activity
on the SDA or SCL pins until V
CC
rises above 2.5V (typical).
This is to ensure that the part does not try to function until
it has enough voltage to do so.
During this time, the 1V precharge circuitry is active and
forces 1V through 200k nominal resistors to the SDA and
SCL pins. Because the I/O card is being plugged into a live
backplane, the voltage on the backplane SDA and SCL
busses may be anywhere between 0V and V
CC
. Precharging
the SCL and SDA pins to 1V minimizes the worst-case
voltage differential these pins will see at the moment of
connection, therefore minimizing the amount of distur-
bance caused by the I/O card.
Once the LTC4301 comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the backplane side to indicate
the completion of a data transaction. When either one
occurs, the part also verifies that both the SDAOUT and
SCLOUT voltages are high. When all of these conditions
are met, the input-to-output connection circuitry is acti-
vated, joining the SDA and SCL busses on the I/O card with
those on the backplane.
Connection Circuitry
Once the connection circuitry is activated, the functional-
ity of the SDAIN and SDAOUT pins is identical. A low
forced on either pin at any time results in both pin voltages
being low. For proper operation, logic low input voltages
should be no higher than 0.4V with respect to the ground
pin voltage of the LTC4301. SDAIN and SDAOUT enter a
logic high state only when all devices on both SDAIN and
SDAOUT release high. The same is true for SCLIN and
SCLOUT. This important feature ensures that clock stretch-
ing, clock synchronization, arbitration and the acknowl-
edge protocol always work, regardless of how the devices
in the system are tied to the LTC4301.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
U
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms as
described here.
Input-to-Output Offset Voltage
When a logic low voltage, V
LOW1
, is driven on any of the
LTC4301’s data or clock pins, the LTC4301 regulates the
voltage on the other side of the device (call it V
LOW2
) at a
slightly higher voltage, as directed by the following
equation:
V
LOW2
= V
LOW1
+ 75mV + (V
CC
/R) • 70Ω (typical)
where R is the bus pull-up resistance in ohms. For ex-
ample, if a device is forcing SDAOUT to 10mV where V
CC
= 3.3V and the pull-up resistor R on SDAIN is 10k, then the
voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 =
108mV (typical). See the Typical Performance Character-
istics section for curves showing the offset voltage as a
function of V
CC
and R.
Propagation Delays
During a rising edge, the rise time on each side is deter-
mined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between
the two sides. This effect is displayed in Figure 1 for
V
CC
= 5V and a 10k pull-up resistor on each side (55pF on
one side and 20pF on the other). SDAIN and SCLIN are
pulled-up to 3.3V, and SDAOUT and SCLOUT are pulled-
up to 5V. Since the output side has less capacitance than
the input, it rises faster and the effective low to high
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