Model 656P/L
Features
Advanced PLL LVPECL or LVDS Clock
Ceramic Surface Mount Package
Low Phase Jitter Performance, 500fs Typical
Advanced PLL Design w/ Low Fundamental Crystal
Frequency Range 10MHz – 1.0GHz *
+2.5V or +3.3V Operation
Output Enable Standard, Pin 2 Option Available
Tape and Reel Packaging, EIA-418
Broadcast Video Systems
Storage Area Networking
Broadband Access
PCI Express
Networking Equipment
Ethernet/GbE/SyncE
Fiber Channel
Test and Measurement
Part Dimensions:
7.0 × 5.0 × 2.0mm
•
178.462mg
Applications
Standard Frequencies
- 25.00MHz
- 125.00MHz
- 27.00MHz
- 148.50MHz
- 50.00MHz
- 153.60MHz
- 74.25MHz
- 155.52MHz
- 100.00MHz
- 156.25MHz
- 106.25MHz
- 200.00MHz
- 250.00MHz
- 312.50MHz
- 322.265625MHz
- 400.00MHz
- 622.08MHz
* See Page 8 for additional developed frequencies.
Check with factory for availability of frequencies not listed.
Description
CTS Model 656P/L is a low cost, high performance PLL clock oscillator supporting differential LVPECL or LVDS
outputs. Employing the latest IC technology, M656P/L has excellent stability and low phase jitter performance.
Ordering Information
Model
656
Output
Type
P
Frequency Code
[MHz]
XXX or XXXX
Frequency
Stability
3
Temperature
Range
I
Supply
Voltage
3
Packaging
T
Code
P
L
E
V
Output
LVPECL - Pin 1 Enable
LVDS - Pin 1 Enable
LVPECL - Pin 2 Enable
LVDS - Pin 2 Enable
Code
6
5
4
3
Stability
±20ppm
2
±25ppm
3
±30ppm
±50ppm
Code
2
3
Voltage
+2.5Vdc
+3.3Vdc
Code
Frequency
Product Frequency Code
1
Notes:
1] Refer to document 016-1454-0, Frequency Code Tables.
3-digits for frequencies <100MHz, 4-digits for frequencies 100MHz or greater.
2] 6I Stability/Temperature combination not available.
3] Check factory availability when paired with 'I' temperature code.
Code Temp. Range
C
-20°C to +70°C
-40°C to +85°C
I
Packing
Code
1k pcs./reel
T
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
This product is specified for use only in standard commercial applications. Supplier disclaims all express and implied warranties and liability in connection with any use of this
product in any non-commercial applications or in any application that may expose the product to conditions that are outside of the tolerances provided in its specification.
DOC# 008-0342-0 Rev. C
Page 1 of 8
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Advanced PLL LVPECL or LVDS Clock
Model 656P/L
Electrical Specifications
Operating Conditions
P ARAMETER
Maximum Supply Voltage
Supply Voltage
Supply Current
LVP ECL
LVDS
O perating Temperature
Storage Temperature
T
A
T
STG
I
CC
SYMBO L
V
CC
V
CC
CO NDITIO NS
-
±5%
MIN
-0.5
2.375
3.135
-
-
-20
-40
-55
TYP
-
2.5
3.3
54
23
+25
-
MAX
4.0
2.625
3.465
88
65
+70
+85
+125
UNIT
V
V
Maximum Load
Maximum Current Value @ +3.3V
mA
°C
°C
-
-
Frequency Stability
P ARAMETER
Frequenc y Range
Frequenc y Stability
[Note 1]
SYMBO L
f
O
Δf/f
O
Δf/f
25
CO NDITIO NS
-
-
First Year @ +25°C, nominal V
CC
MIN
TYP
10 - 1000
20, 25 or 50
MAX
UNIT
MHz
±ppm
Aging
-3
-
3
ppm
1.] Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
Output Parameters
P ARAMETER
O utput Type
O utput Load
O utput Voltage Levels
O utput Duty Cyc le
Rise and Fall Time
O utput Type
O utput Load
O utput Voltage Levels
O utput Duty Cyc le
Differential O utput Voltage
O ffset Voltage
Rise and Fall Time
SYMBO L
-
R
L
V
OH
V
OL
SYM
T
R
, T
F
-
R
L
V
OH
V
OL
SYM
V
OD
V
OS
T
R
, T
F
CO NDITIO NS
-
Terminated to V
CC
- 2.0V
PECL Load
@ V
CC
- 1.3V
@ 20%/80% Levels, R
L
= 50 Ohms
-
Between Outputs
LVDS Load
@ 1.25V
R
L
= 100 Ohms
LVDS Load
@ 20%/80% Levels, R
L
= 100 Ohms
-
-
0.90
45
175
1.20
-
-
V
CC
- 1.03
V
CC
- 1.85
45
-
MIN
TYP
LVP ECL
50
-
-
-
0.25
LVDS
100
1.43
1.10
-
330
1.25
-
-
1.60
-
55
454
1.30
0.5
-
V
CC
- 0.60
V
CC
- 1.60
55
0.60
MAX
UNIT
-
Ohms
V
%
ns
-
Ohms
V
%
mV
V
ns
DOC# 008-0342-0 Rev. C
Page 2 of 8
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Advanced PLL LVPECL or LVDS Clock
Model 656P/L
Electrical Specifications
Output Parameters
P ARAMETER
Start Up Time
Enable Func tion [Tri-State]
Enable Input Voltage
Disable Input Voltage
Disable Current
Enable Time
P hase Jitter, RMS
P eriod Jitter, RMS
P eriod Jitter, pk-pk
V
IH
V
IL
I
IL
T
PLZ
tjrms
pjrms
pjpk-pk
Pin 1 or 2 Logic '1', Output Enabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '1', Output Enabled
Bandwidth 12 kHz - 20 MHz
-
-
0.7V
CC
-
-
-
-
-
-
-
-
16
-
500
2.5
25
-
0.3V
CC
22
200
<1000
-
-
V
V
mA
ns
fs
ps
ps
SYMBO L
T
S
CO NDITIO NS
Application of V
CC
MIN
-
TYP
3
MAX
5
UNIT
ms
Enable Truth Table
Pin 1 or Pin 2
Logic ‘1’
Open
Logic ‘0’
Pin 4 & Pin 5
Output
Output
High Imp.
Test Circuit
LVPECL
LVDS
Output Waveform
LVPECL or LVDS
DOC# 008-0342-0 Rev. C
Page 3 of 8
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Advanced PLL LVPECL or LVDS Clock
Model 656P/L
Electrical Specifications
Performance Data
Phase Noise [typical]
100.00MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
156.25MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
312.50MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
800.00MHz, LVPECL, V
CC
= 3.3V, T
A
= +25°C
DOC# 008-0342-0 Rev. C
Page 4 of 8
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Advanced PLL LVPECL or LVDS Clock
Model 656P/L
Electrical Specifications
Performance Data
Phase Noise Tabulated
Typical, HCMOS, V
CC
= 3.3V, T
A
= +25°C
P ARAMETER
LVP ECL @ 1 0 0 .0 0 MHz
P hase Noise
Single Side Band
@ 10Hz
@ 100Hz
@ 1kHz
-
@ 10kHz
@ 100kHz
@ 1MHz
@ 10MHz
@ 40MHz
P hase Jitter, RMS
P ARAMETER
LVP ECL @ 3 1 2 .5 0 MHz
P hase Noise
Single Side Band
@ 10Hz
@ 100Hz
@ 1kHz
-
@ 10kHz
@ 100kHz
@ 1MHz
@ 10MHz
@ 40MHz
P hase Jitter, RMS
tjrms
-81.30
-91.80
-105.30
-115.50 dBc/Hz
-120.80
-136.40
-153.20
-153.20
fs
P hase Jitter, RMS
tjrms
-
tjrms
SYMBO L
-69.70
-92.90
-115.90
-126.80 dBc/Hz
-129.50
-143.50
-154.90
-155.30
fs
UNIT
P hase Jitter, RMS
P ARAMETER
LVP ECL @ 8 0 0 .0 0 MHz
P hase Noise
Single Side Band
@ 10Hz
@ 100Hz
@ 1kHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 10MHz
@ 40MHz
-85.00
-90.90
-96.90
-106.70 dBc/Hz
-107.50
-125.90
-145.40
-150.40
fs
tjrms
SYMBO L
-
SYMBO L
CO NDITIO NS
TYP
UNIT
P ARAMETER
LVP ECL @ 1 5 6 .2 5 MHz
P hase Noise
Single Side Band
@ 10Hz
@ 100Hz
@ 1kHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 10MHz
@ 40MHz
-88.60
-97.80
-111.40
-121.00 dBc/Hz
-127.00
-141.80
-151.50
-153.30
fs
UNIT
SYMBO L
CO NDITIO NS
TYP
UNIT
Integration Bandwidth 12kHz - 20MHz 714.35
CO NDITIO NS
TYP
Integration Bandwidth 12kHz - 20MHz 869.93
CO NDITIO NS
TYP
Integration Bandwidth 12kHz - 20MHz 496.03
Integration Bandwidth 12kHz - 20MHz 781.63
DOC# 008-0342-0 Rev. C
Page 5 of 8
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
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