74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Rev. 10 — 2 April 2012
Product data sheet
1. General description
The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for
V
CC
operation at 3.3 V.
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state
outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (nCP), the nQn outputs of the flip-flop take on the logic
levels set up at the nDn inputs.
2. Features and benefits
16-bit edge-triggered flip-flop
3-state buffers
Output capability: +64 mA and
32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
JESD78B Class II exceeds 500 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Nexperia
74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVT16374ADL
74LVT16374ADGG
74LVTH16374ADGG
74LVT16374AEV
74LVTH16374ABX
40 C
to +85
C
40 C
to +125
C
VFBGA56
HXQFN60
40 C
to +85
C
40 C
to +85
C
Name
SSOP48
TSSOP48
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
plastic very thin fine-pitch ball grid array
package; 56 balls; body 4.5
7
0.65 mm
plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4
6
0.5 mm
Version
SOT370-1
SOT362-1
SOT702-1
SOT1134-2
Type number
4. Functional diagram
47
46
44
43
41
40
38
37
1
1OE
48
1CP
24
2OE
25
2CP
1D0
1D1
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
001aaa254
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
1
1CP
1OE
EN1
C3
EN2
C4
3D
1
2
3
5
6
8
9
11
12
4D
2
13
14
16
17
19
20
22
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
1D2
1D3
2
3
5
6
8
9
11
12
1D4
1D5
36
35
33
32
30
29
27
26
1D6
1D7
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
2D0
2D1
2D2
25
24
2CP
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
2D3
2D4
2D5
2D6
13
14
16
17
19
20
22
23
2D7
001aac369
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVT_LVTH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 10 — 2 April 2012
2 of 19
Nexperia
74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
nD0
D
nD1
D
nD2
D
nD3
D
nD4
D
nD5
D
nD6
D
nD7
D
CP
nCP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
001aac371
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
74LVT16374A
74LVTH16374A
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48 1CP
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 V
CC
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 V
CC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2CP
001aak263
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
V
CC
18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
ball A1
index area
A
B
C
D
E
F
G
H
J
K
74LVT16374A
74LVTH16374A
1 2 3 4 5 6
001aak264
Transparent top view
Fig 4.
Pin configuration for SOT370-1 (SSOP48) and
SOT362-1 (TSSOP48)
Fig 5.
Pin configuration for SOT702-1 (VFBGA56)
74LVT_LVTH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 10 — 2 April 2012
3 of 19
Nexperia
74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
terminal 1
index area
D1
A32
A31
A30
A29
A28
A27
D4
A1
D5
B20
B19
B18
D8
A26
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
GND
(1)
B11
B12
B15
B16
B17
A25
A24
A23
A22
74LVT16374A
74LVTH16374A
B14
A21
B13
A20
A19
A18
A10
D6
B8
B9
B10
D7
A17
D2
A11
A12
A13
A14
A15
A16
D3
001aak265
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 6.
Pin configuration SOT1134-2 (HXQFN60)
74LVT_LVTH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 10 — 2 April 2012
4 of 19
Nexperia
74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
SOT370-1 and
SOT362-1
1OE, 2OE
1CP, 2CP
1Q0 to 1Q7
2Q0 to 2Q7
GND
V
CC
1D0 to 1D7
2D0 to 2D7
n.c.
1, 24
48, 25
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20,
22, 23
SOT702-1
A1, K1
A6, K6
B2, B1, C2, C1, D2,
D1, E2, E1
F1, F2, G1, G2, H1,
H2, J1, J2
SOT1134-2
A30, A13
A29, A14
output enable input (active LOW)
clock input
Description
B20, A31, D5, D1, A2, data output
B2, B3, A5
A6, B5, B6, A9, D2,
D6, A12, B8
data output
4, 10, 15, 21, 28, 34, 39, B3, D3, G3, J3, J4,
45
G4, D4, B4
7, 18, 31, 42
47, 46, 44, 43, 41, 40,
38, 37
36, 35, 33, 32, 30, 29,
27, 26
-
C3, H3, H4, C4
B5, B6, C5, C6, D5,
D6, E5, E6
F6, F5, G6, G5, H6,
H5, J6, J5
A2, A3, A4, A5,
K2, K3, K4, K5
A32, A3, A8, A11, A16, ground (0 V)
A19, A24, A27
A1, A10, A17, A26
B18, A28, D8, D4,
A25, B16, B15, A22
A21, B13, B12, A18,
D3, D7, A15, B10
A4, A7, A20, A23, B1,
B4, B7, B9, B11, B14,
B17, B19
supply voltage
data input
data input
not connected
6. Functional description
Table 3.
Function table
[1]
Input
nOE
Load and read register
Hold
Disable outputs
L
L
L
H
H
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
= LOW-to-HIGH clock transition.
Operating mode
Internal register
nCP
NC
NC
nDn
l
h
X
X
nDn
L
H
NC
NC
nDn
Output
nQ0 to nQ7
L
H
NC
Z
Z
74LVT_LVTH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 10 — 2 April 2012
5 of 19
FPGA/CPLD
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