DDR3-1066 1GB SO-DIMM 204PIN
With PROMOS 128Mx8 DRAM
D3SP28081XH18AC
Specifications
Density:
Pin Count:
Version:
Type:
Speed:
Component Config:
1GB
204-pin
Unbuffered
SO-DIMM
PC3-8500
128Meg x 8
Data Rate:
CAS Latency:
Voltage:
PCB Layers:
ECC :
Module Ranks :
1066 Mbps
7
1.5V
6
Non-ECC
Single Rank
Features
‧
Data rate:1066Mbps
‧
Power supply: VDD= 1.5V + 0.075V
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
Interface: SSTL_15
/CAS Latency(CL):5,6,7,8,9
/CAS write latency(CWL):5,6,7
Fully differential clock inputs (CK, /CK) operation
Differential Data Strobe (DQS, /DQS)
DM masks write data-in at the both rising and falling edges of the data strobe
BL switch on the fly
8banks
8K refresh cycles /64ms
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
Refresh: Auto-Refresh, Self-Refresh
On Die Thermal Sensor supported(JEDEC optional)
8 bit pre-fetch
Lead-Free Products are RoHS compliant
Average Refresh Period 7.8us at 0℃≦TC≦85℃
3.9us at
85℃＜TC≦95℃
1
REV 3.0
DDR3-1066 1GB SO-DIMM 204PIN
With PROMOS 128Mx8 DRAM
D3SP28081XH18AC
Description
The D3SP28081XH18AC is 128M words X 64 bits, 1 ranks . Unbuffered Small Outline Dual
In-Line Memory Module (SO-DIMM) .DDR3 SDRAMs in Fine Ball Grid Array(FBGA) packages on a
204pin glass-epoxy substrate. Provide a high performance 8 byte interface in 67.60mm width form
factor of industry standard. It is suitable for easy interchange and addition.
Speed Grade & Key Parameters
Speed
CL-tRCD-tRP
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
tRCF(min)
tRRD(min)
tFAW(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
110
10
40
DDR3-1066
7-7-7
1.875
7
13.13
13.13
37.5
50.625
110
7.5
37.5
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
110
6.0
30
Unit
ns
tCK
ns
ns
ns
ns
ns
ns
ns
Address Configuration
512MB
Organization
Refresh Method
Row Address
Column address
Bank Address
Auto Precharge
# of Rank
# of DRAMs
64M X 64
8K/64ms
A0-A12
A0-A9
BA0-BA2
A10
1
4
1GB
128M X 64
8K/64ms
A0-A13
A0-A9
BA0-BA2
A10
1
8
1GB
128M X 72
8K/64ms
A0-A13
A0-A9
BA0-BA2
A10
1
9
2GB
256M X 64
8K/64ms
A0-A13
A0-A9
BA0-BA2
A10
2
16
2GB
256M X 72
8K/64ms
A0-A13
A0-A9
BA0-BA2
A10
2
18
2
REV 3.0
DDR3-1066 1GB SO-DIMM 204PIN
With PROMOS 128Mx8 DRAM
D3SP28081XH18AC
Absolute Maximum ratings
Parameter
Voltage on V
DD
pin relative to Vss
Voltage on V
DDQ
pin relative to Vss
Input voltage
Output voltage
Storage Temperature
Operating case temperature
Storage Humidity
Power dissipation
Short circuit output current
Symbol
VDD
VDDQ
Vin
V
OUT
T
STG
Toper
H
STG
PD
IOUT
Rating
-0.4V ~ +1.975V
-0.4V ~ +1.975V
-0.4V ~ +1.975V
-0.4V ~ +1.975V
-55 to +100
0 to 95
5 to 95
9
50
Units
V
V
V
V
℃
℃
%
W
mA
Notes
1
2,3
Note:
1. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
2.
The Normal Temperature Range specifies the temperatures where all DRAM specifications will be
supported. During operation, the DRAM case temperature must be maintained between 0-85℃ under all
operating conditions.
3.
Some applications require operation of the Extended Temperature Range between 85℃ and 95℃ case
temperature. Full specifications are guaranteed in this range, but the following additional conditions
apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to
3.9us. It is also possible to specify a component with 1X refresh(tREFI to 7.8us) in the Extended
Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to
either use the Manual Self-Refresh mode with Extended Temperature Range capability(MR2A6=0b
and MR2A7=1b) or enable the optional Auto Self-Refresh mode(MR2A6=1b and MR2A7=0b)
3
REV 3.0
DDR3-1066 1GB SO-DIMM 204PIN
With PROMOS 128Mx8 DRAM
D3SP28081XH18AC
Recommended DC Operating Conditions(SSTL-15)
Symbol
VDD
VDDQ
VSS
VDDSPD
VREFCA(DC)
VREFDQ(DC)
Parameter
Supply Voltage
Supply Voltage for Output
Supply Voltage
Supply Voltage
Input reference voltage
Input reference voltage for DQ
Rating
Min.
1.425
1.425
0
3.0
0.49xVDDQ
0.49xVDDQ
Typ.
1.5
1.5
0
3.3
0.50xVDDQ
0.50xVDDQ
Max
1.575
1.575
0
3.6
0.51xVDDQ
0.51xVDDQ
Units
V
V
V
V
V
V
Notes
1,2
1,2
1
1
1
Note:
1. DDR3 SDRAM component specification.
2. Under all conditions VDDQ must be less than or equal to VDD.
Pin Description
Pin Name
A0~A9,A11
A13-A15
A10(AP)
A12(/BC)
/RAS
/CAS
/WE
/CS0-/CS1
Description
Address intput
Auto precharge
Bust chop
SDRAM Row address strobe
SDRAM Column address strobe
SDRAM write enable
Chip select
Pin Name
V
REFCA
V
REFDQ
/CK0,/CK1
CK0,CK1
SCL
SDA
SA0-SA1
VDD*
VDDQ*
VREF
VSS
VDDSPD
NC
/RESET
TEST
/EVENT
Description
Input/Output voltage reference
SDRAM differential clock input
SDRAM clocks input
Clock input for serial PD
Data intput/output for serial PD
Serial address select intput
SDRAM core power supply
SDRAM I/O Driver power supply
SDRAM I/O reference supply
Ground
Serial EEPROM positive power supply
No connection
Set DRAM to known state
Used by memory bus analysis tools(unused on
memory DIMMs)
Temperature event pin
CKE0,CKE1
SDRAM clock enable
ODT0,ODT1
On-die termination control
DQ0-DQ63
BA0-BA2
Data input/output
SDRAM bank addresses
DQS0-DQS7
Input and output data strobe
DM0-DM7
SDRAM data mask /high data strobe
/DQS0-/DQS7
Input and output data strobe
VTT
SDRAM I/O termination supply
4
REV 3.0
DDR3-1066 1GB SO-DIMM 204PIN
With PROMOS 128Mx8 DRAM
D3SP28081XH18AC
Pin Configuration
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
Front
V
REFD
Vss
DQ0
DQ1
Vss
DM0
Vss
DQ2
DQ3
Vss
DQ8
DQ9
Vss
/DQS1
DQS1
Vss
DQ10
DQ11
Vss
DQ16
DQ17
Vss
/DQS2
DQS2
Vss
DQ18
DQ19
Vss
DQ24
DQ25
Vss
DM3
Vss
DQ26
DQ27
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
Front
Vss
DQ4
DQ5
Vss
/DQS0
DQS0
Vss
DQ6
DQ7
Vss
DQ12
DQ13
Vss
DM1
/RESE
Vss
DQ14
DQ15
Vss
DQ20
DQ21
Vss
DM2
Vss
DQ22
DQ23
Vss
DQ28
DQ29
Vss
/DQS3
DQS3
Vss
DQ30
DQ31
Pin
71
Front
Vss
KEY
Pin
72
Front
Vss
Pin
139
141
Front
Vss
DQ34
DQ35
Vss
DQ40
DQ41
Vss
DM5
Vss
DQ42
DQ43
Vss
DQ48
DQ49
Vss
/DQS6
DQS6
Vss
DQ50
DQ51
Vss
DQ56
DQ57
Vss
DM7
Vss
DQ58
DQ59
Vss
SA0
V
DDSPD
SA1
V
TT
Pin
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
Front
DQ38
DQ39
Vss
DQ44
DQ45
Vss
/DQS5
DQS5
Vss
DQ46
DQ47
Vss
DQ52
DQ53
Vss
DM6
Vss
DQ54
DQ55
Vss
DQ60
DQ61
Vss
/DQS7
DQS7
Vss
DQ62
DQ63
Vss
NC
SDA
SCL
V
TT
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
CKE0
VDD
NC
BA2
VDD
A12/BC
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
/CK0
VDD
A10/AP
BA0
VDD
/WE
/CAS
VDD
A13
/S 1
VDD
TEST
Vss
DQ32
DQ33
Vss
/DQS4
DQS4
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
/CK1
VDD
BA1
/RAS
VDD
/S 0
ODT0
VDD
ODT1
NC
VDD
V
REFCA
Vss
DQ36
DQ37
Vss
DM4
Vss
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
5
REV 3.0
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