Product Specification
PE42850
Product Description
The PE42850 is a HaRP™ technology-enhanced SP5T
high power RF switch supporting wireless applications up
to 1 GHz. It offers maximum power handling of 42.5 dBm
continuous wave (CW). It delivers high linearity and
excellent harmonics performance. It has both a standard
and attenuated RX mode. No blocking capacitors are
required if DC voltage is not present on the RF ports.
The PE42850 is manufactured on Peregrine’s
UltraCMOS
®
process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
Figure 1. Package Type
32-lead 5 × 5 mm QFN
UltraCMOS
®
SP5T RF Switch
30–1000 MHz
Features
Dual mode operation: SP5T or SP3T
HaRP™ technology enhanced
Fast settling time
No gate and phase lag
No drift in insertion loss and phase
Up to 45 dBm instantaneous power
in 50Ω
Up to 40 dBm instantaneous power
< 8:1 VSWR
36 dB TX to RX isolation
Low harmonics of 2f
o
and 3f
o
= –90 dBc
(1.15:1 VSWR)
ESD performance
1.5 kV HBM on all pins
Figure 2. Functional Diagram of SP3T
Configuration
Figure 3. Functional Diagram of SP5T
Configuration
ANT can be tied to TX1 and TX2 or TX3 and TX4
SP5T, standard configuration
DOC-02178
Document No. DOC-81084-1
│
www.psemi.com
©2012-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 12
PE42850
Product Specification
Table 1. Electrical Specifications @ –40 to +85 °C, V
DD
= 2.3–5.5V, V
SS_EXT
= 0V or V
DD
= 3.4–5.5V,
V
SS_EXT
= –3.4V (Z
S
= Z
L
= 50Ω), unless otherwise noted
1
Parameter
Operating frequency
Active TX port 1, 2, 3 or 4 @ rated power (–40 °C, +25 °C)
30–520 MHz
520–1000 MHz
Active TX port 1, 2, 3 or 4 @ rated power (+85 °C)
30–520 MHz
520–1000 MHz
Active RX port (–40 °C, +25 °C)
30–520 MHz
520–1000 MHz
ANT–RX
Active RX port (+85 °C)
30–520 MHz
520–1000 MHz
1575 MHz for GPS RX, < –10 dBm, +25 °C
Insertion loss
2
(attenuated state)
Isolation (supply biased)
Isolation (supply biased)
Unbiased isolation
V
DD
, V1, V2, V3 = 0V
Unbiased isolation
V
DD
, V1, V2, V3 = 0V
ANT–RX
TX–TX
TX–RX
ANT–TX
ANT–RX
Active RX port
30–1000 MHz
30–520 MHz
520–1000 MHz
30–520 MHz
520–1000 MHz
+27 dBm
+27 dBm
Un-attenuated state
30–520 MHz
520–1000 MHz
Return loss
2
ANT–RX
Un-attenuated state, 1575 MHz for GPS RX, < –10 dBm, +25 °C
Attenuated state, optimized without attenuator engaged
30–520 MHz
520–1000 MHz
Return loss
2
2nd and 3rd harmonic
(< 1.15:1 VSWR)
2nd and 3rd harmonic
(< 8:1 VSWR)
2nd and 3rd harmonic
(50Ω source/load impedance)
2nd and 3rd harmonic
(50Ω source/load impedance)
Input 0.1dB compression point
4
IIP3
Settling time
Switching time
ANT–TX
TX
30–520 MHz
520–1000 MHz
30–520 MHz @ +40.0 dBm
521–870 MHz @ +38.5 dBm
871–1000 MHz @ +37.5 dBm
30–520 MHz @ +40.0 dBm (pulsed signal, at 10% duty cycle
3
)
521–870 MHz @ +38.5 dBm (pulsed signal, at 10% duty cycle
3
)
871–1000 MHz @ +37.5 dBm (pulsed signal, at 10% duty cycle
3
)
30–1000 MHz @ +45.0 dBm (pulsed signal, at 10% duty cycle
3
)
30–1000 MHz @ +42.5 dBm (CW)
1000 MHz
Un-attenuated state
Attenuated state
From 50% control until harmonics within specifications
50% CTRL to 90% or 10% RF
42
33
30
15
70
15.2
33
29
34
29
6
14
22
18
10
16
13
21
15
27
22
14
21
18
28
17
–90
–81
Path
Condition
Min
30
0.25
0.35
0.30
0.45
0.50
0.65
0.60
0.70
1
16
36
30
36
30
Typ
Max
1000
0.30
0.45
0.35
0.55
0.60
0.80
0.70
0.85
1.2
16.8
Unit
MHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBc
Insertion loss
2
ANT–TX
Insertion loss
2
(un-attenuated state)
TX
TX
TX
ANT–TX
RX
–82
–80
–84
45.5
–74
–71
–75
dBc
dBc
dBc
dBm
dBm
dBm
µs
µs
Notes: 1. In a 2TX–1RX SP3T configuration, TX1 and TX2 are tied and TX3 and TX4 are tied respectively. Refer to Application Note AN35 for SP3T performance data.
2. Narrow trace widths are used near each port to improve impedance matching. Refer to evaluation board layouts (Figure
23)
and schematic (Figure
24)
for details.
3. 10% of 4620 µs period.
4. The input 0.1dB compression point is a linearity figure of merit. Refer to
Table 3
for the RF input power P
IN.
©2012-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 12
Document No. DOC-81084-1
│
UltraCMOS
®
RFIC Solutions
PE42850
Product Specification
Figure 4. Pin Configuration (Top View)*
32
GND
31
GND
30
GND
29
GND
27
GND
26
GND
25
GND
28
ANT
Table 3. Operating Ranges
1
Parameter
Supply voltage (normal
mode, V
SS_EXT
= 0V)
Supply voltage (bypass
mode, V
SS_EXT
= –3.4V,
V
DD
≥
3.4V for full spec.
compliance)
Negative supply voltage
(bypass mode)
Supply current (normal
mode, V
SS_EXT
= 0V)
Supply current (bypass
mode, V
SS_EXT
= –3.4V)
Negative supply current
(bypass mode, V
SS_EXT
=
–3.4V)
Symbol
V
DD
Min
2.3
Typ
Max
5.5
Unit
V
V
DD
2.7
3.4
5.5
V
V
SS_EXT
I
DD
I
DD
I
SS
V
IH
V
IL
P
IN–TX
P
IN–TX
–3.6
130
50
–40
–16
–3.2
200
80
V
µA
µA
µA
10
11
12
13
14
15
16
9
GND
GND
GND
V
SS_EXT
V3
V2
V
DD
V1
Digital input high
(V1, V2, V3)
Digital input low
(V1, V2, V3)
TX RF input power
2,3
(VSWR
≤
8:1)
TX RF input power
2,3
(50Ω source/load
impedance)
TX RF input power
2
(50Ω source/load
impedance, CW)
ANT RF input power,
unbiased (VSWR
≤
8:1)
RX RF input power
2
(VSWR
≤
8:1)
Operating temperature
range (case)
Operating junction
temperature
1.17
–0.3
3.6
0.6
40
V
V
dBm
Note: * Pins 1, 3, 5, 7, 9, 10, 17, 19, 20, 22, 24, 26, 27, 29, 30 and 31 can be
N/C if deemed necessary by the customer.
Table 2. Pin Descriptions
Pin #
1, 3, 5–7, 9–
11, 17–20,
22, 24–27,
29–32
2
4
8
12
13
14
15
16
21
23
28
Pad
Notes:
Pin Name
Description
45
dBm
GND
TX1
2
TX2
1,2
RX
2
Ground
P
IN–TX
P
IN–ANT
P
IN–RX
T
OP
T
j
–40
42.5
dBm
Transmit pin 1
Transmit pin 2
Receive pin
Supply voltage (nominal 3.3V)
Digital control logic input 3
Digital control logic input 2
Digital control logic input 1
External V
SS
negative voltage control
Transmit pin 3
Transmit pin 4
Antenna pin
Exposed pad: ground for proper operation
27
27
85
135
dBm
dBm
°C
°C
V
DD
V3
V2
V1
V
SS_EXT3
TX3
2
TX4
1,2
ANT
2
GND
Notes: 1. In a 2TX–1RX SP3T configuration, TX1 and TX2 are tied and TX3
and TX4 are tied respectively. Refer to Application Note AN35 for
SP3T performance data.
2. Supply biased.
3. Pulsed, 10% duty cycle of 4620 µs period.
1. To operate the part as a 2TX–1RX SP3T, tie TX1 to TX2 and TX3
to TX4 respectively. Refer to Application Note AN35 for SP3T
performance data.
2. RF pins 2, 4, 8, 21, 23 and 28 must be at 0 VDC. The RF pins do
not require DC blocking capacitors for proper operation if the 0 VDC
requirement is met.
3. Use V
SS_EXT
(pin 16, V
SS_EXT
= –V
DD
) to bypass and disable internal
negative voltage generator. Connect V
SS_EXT
(pin 16) to GND (V
SS_EXT
= 0V) to enable internal negative voltage generator.
Document No. DOC-81084-1
│
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©2012-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 12
PE42850
Product Specification
Table 4. Absolute Maximum Ratings
Parameter/Condition
Supply voltage
Digital input voltage
(V1, V2, V3)
TX RF input power
1
(50Ω
source/load impedance)
TX RF input power
1
(VSWR
≤
8:1)
ANT RF input power, unbiased
(VSWR
≤
8:1)
RX RF input power
1
(VSWR
≤
8:1)
Storage temperature range
Maximum case temperature
Peak maximum junction
temperature
(10 seconds max)
ESD voltage HBM
2
, all pins
ESD Voltage MM
3
, all pins
Symbol
V
DD
V
CTRL
P
IN–TX
P
IN–TX
P
IN–ANT
P
IN–RX
T
ST
T
CASE
T
j
V
ESD
V
ESD
–65
Min
–0.3
–0.3
Max
5.5
3.6
45
40
27
27
150
85
200
1500
200
Unit
V
V
dBm
dBm
dBm
dBm
°C
°C
Switching Frequency
The PE42850 has a maximum 10 kHz switching
rate when the internal negative voltage generator
is used (pin 16 = GND). The rate at which the
PE42850 can be switched is only limited to the
switching time (Table
1)
if an external negative
supply is provided (pin 16 = V
SS_EXT
).
Switching frequency describes the time duration
between switching events. Switching time is the
time duration between the point the control signal
reaches 50% of the final value and the point the
output signal reaches within 10% or 90% of its
target value.
Optional External V
SS
Control (V
SS_EXT
)
°C
V
V
Notes: 1. Supply biased
2. Human Body Model (MIL-STD 883 Method 3015)
3. Machine Model (JEDEC JESD22-A115)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
5x5 mm QFN package is MSL3.
For proper operation, the V
SS_EXT
control pin must
be grounded or tied to the Vss voltage specified in
Table 3.
When the V
SS_EXT
control pin is grounded,
FETs in the switch are biased with an internal
voltage generator. For applications that require the
lowest possible spur performance, V
SS_EXT
can be
applied externally to bypass the internal negative
voltage generator.
Spurious Performance
The typical spurious performance of the PE42850
is –130 dBm when V
SS_EXT
= 0V (pin 16 = GND). If
further improvement is desired, the internal
negative voltage generator can be disabled by
setting V
SS_EXT
= –3.4V.
Table 5. Truth Table
Path
ANT – RX Attenuated
ANT – TX1
ANT – TX2
ANT – TX1 and TX2*
ANT – RX
ANT – TX3
ANT – TX4
ANT – TX3 and TX4*
V3
L
L
L
L
H
H
H
H
V2
L
L
H
H
L
L
H
H
V1
L
H
L
H
L
H
L
H
Note: * In a 2TX–1RX SP3T configuration, TX1 and TX2 are tied and TX3 and
TX4 are tied respectively. Refer to Application Note AN35 for SP3T
performance data.
©2012-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 12
Document No. DOC-81084-1
│
UltraCMOS
®
RFIC Solutions
PE42850
Product Specification
Typical Performance Data @ +25 °C and V
DD
= 3.4V, unless otherwise specified
Figure 5. Insertion Loss vs. Temp (TX)
Figure 6. Insertion Loss vs. V
DD
(TX)
Figure 7. Insertion Loss vs. Temp
(RX, Un-Attenuated)
Figure 8. Insertion Loss vs. V
DD
(RX, Un-Attenuated)
Figure 9. Insertion Loss vs. Temp
(RX, Attenuated)
Figure 10. Insertion Loss vs. V
DD
(RX, Attenuated)
Document No. DOC-81084-1
│
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©2012-2016 Peregrine Semiconductor Corp. All rights reserved.
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