ICS1523
Video Clock Synthesizer with I
2
C Programmable Delay
General Description
The ICS1523 is a low-cost, high-performance
frequency generator. It is well suited to general
purpose phase controlled clock synthesis as well as
line-locked and genlocked high-resolution video
applications. Using IDT’s advanced low-voltage
CMOS mixed-mode technology, the ICS1523 is an
effective phase controlled clock synthesizer and also
supports video projectors and displays at resolutions
from VGA to beyond UXGA.
The ICS1523 offers clock outputs in both differential
(to 250 MHz) and single-ended (to 150 MHz) formats.
Dynamic Phase Adjust (DPA) allows I
2
C™ control of
the output clock’s phase relative to the input sync
signal. A second, half speed set of outputs that can be
separately enabled allows such applications as
clocking analog-to-digital converters. The FUNC pin
provides either the regenerated input from the
phase-locked loop (PLL) divider chain output, or the
input HSYNC after being sharpened by the Schmitt
trigger. Both signals are then delayed by the DPA.
The advanced PLL uses either its internal
programmable feedback divider or an external divider.
Either the internal or external loop filters is software
selectable. The COAST input pin disables the PLL’s
charge pump, causing the device to idle at the current
speed for short periods of time, such as vertical
blanking intervals.
The device is programmed by a standard I
2
C-bus
serial interface and is available in a 24-pin, wide
small-outline integrated circuit (SOIC) package.
Features
• Low Jitter
• Wide input frequency range
• 15.734 kHz to 100 MHz
• PECL differential outputs
• Up to 250 MHz
• SSTL_3 Single-ended clock outputs
• Up to 150 MHz
• Dynamic Phase Adjust (DPA) for all outputs
• I
2
C controlled phase adjustment
• Full clock cycle down to 1/64 of a clock
• Double-buffered control registers
• External or internal loop filter selection
• COAST input can disable charge pump
• 3.3 VDD
• 5 volt Tolerant Inputs
• Industry Standard I
2
C-bus programming interface
• PLL Lock detection via I
2
C or LOCK/REF output pin
• 24-pin 300-mil SOIC package
Applications
• Frequency synthesis
• LCD monitors, video projectors and plasma displays
• Genlocking multiple video subsystems
Pin Configuration
ICS1523 Functional Diagram
External Loop Filter (optional)
OSC
HSYNC
I
2
C I/F
CLK
CLK/2
FUNC
24-pin SOIC
MDS ICS1523 ZC
1
Integrated Device Technology, Inc.
Tech Support: www.idt.com/go/clockhelp
Revision 020811
ICS1523
Video Clock Synthesizer with I
2
C Programmable Delay
Section 1
Operational Description
Figure 1-1
PLL Functional Blocks
1.1 Naming Conventions
0xY = Register Index Y(hex)
0xY:Z = Register Index Y(hex), bit Z
0xY:Z~Q = Register Index Y(hex), bit Z to Q
1.2 Overview
The ICS1523 is a general purpose, high-performance,
I2C programmable clock generator. It also addresses
stringent graphics system line-locked and genlocked
applications and provides the clock signals required by
high-performance analog-to-digital converters.
Included are a phase-locked loop (PLL) with an over
500MHz voltage controlled oscillator (VCO), a Dynamic
Phase Adjust to provide (DPA) output clocks with a
programmable phase delay with respect to the input
HSYNC. This delay occurs on all PLL outputs including
the differential (PECL) and single-ended (SSTL_3)
high-speed clock outputs and the FUNC output.
The ICS1523 has the ability to operate in line-locked
mode with the HSYNC input or in frequency synthesis
mode with the OSC input with a 7 bit input divider. See
Section 6, “OSC Divider and REF”
1.4 Voltage Controlled Oscillator (VCO)
The heart of the ICS1523 is a VCO. The VCOs speed
is controlled by the voltage on the loop filter circuit. This
voltage is controlled by the charge pump (CP) and will
be further described later in this section.
1.3 Phase-Locked Loop (PLL)
The phase-locked loop has a very wide input frequency
range (8 kHz to 100 MHz). Not only is the ICS1523 an
excellent, general purpose clock synthesizer, but it is
also capable of line-locked operation.
1.5 Charge Pump (CP) and COAST Input
The CPen bit and COAST input pin can enable and
disable the Charge Pump as needed. See Register
0:7-6. This is for maintaining the correct speed clock
outputs in the absence of reliable HSYNC inputs and is
useful for skipping vertical blanking intervals. These
intervals can have double frequency serration pulses or
even be missing HSYNC pulses completely. The
charge pump is asynchronously disabled and
synchronously re-enabled on the second input HSYNC
after the disable signal goes invalid.
1.6 VCO Divider (VCOD)
The VCOs clock output is first passed through the VCO
Divider (VCOD). The VCOD allows the VCO to operate
at higher speeds than the required output clock. The
VCOD has no effect on the speed of the output clocks,
but it increases the VCO frequency, thereby reducing
jitter and allowing VCO operation between 100 to 500
MDS ICS1523 ZC
2
Integrated Device Technology, Inc.
Tech Support: www.idt.com/go/clockhelp
Revision 020811
ICS1523
Video Clock Synthesizer with I
2
C Programmable Delay
MHz even if a low output frequency is required.The
output of the VCOD is the full speed output frequency
seen on the CLK pins.
1.11 OSC Input
The high-frequency OSC input pin, has a 7-bit user
programmable divider. OSC can also be selected as
the loop input, allowing the loop to operate from any
appropriate, single-ended source, typically a crystal
oscillator.
1.7 Dynamic Phase Adjust (DPA)
The VCOD output clock is then sent through the DPA
for phase adjustment relative to the input HSYNC as
well as the 12-bit internal Feedback Divider. An
external divider may alternately be used and it’s output
must be input on the EXTFB pin. The feedback divider
controls how many clocks are seen during every cycle
of the input reference.
The DPA allows a programmable delay between the
input HSYNC to the clock and FUNC outputs, relative
to the input HSYNC signal on a sub-pixel basis. A delay
of up to one clock period is programmable: See Note 6
in
Section 5, “Register Set Details”
for more
information.
1.12 FUNC Output
Either the conditioned HSYNC input or the loop output
(recovered HSYNC) is available at the FUNC pin, and
is aligned with the output clocks.
1.13 Logic Inputs
The ICS1523 uses Low-Voltage TTL (LVTTL) inputs
that are 5 volt tolerant such as most VESA compliant
HSYNC and VSYNC signals.
1.8 Feedback Divider (FD) and FUNC
The 12-bit FD controls how many clocks are seen
between successive HSYNCs.
The number of clocks per HSYNC is FB + 8
The FD output is a 4 CLK wide, active high signal
called FUNC. The FUNC signal is aligned with the
output clocks via the DPA and is intended to be used by
the system as a replacement for the HSYNC input,
which is of in-determinate quality and is not aligned
with the output clocks. Alternately, the post
Schmitt-trigger HSYNC signal can also be DPA
delayed and then output on the FUNC pin. See 0x0:5.
1.14 Output Drivers
The ICS1523 also has SSTL_3 (EIA/JESD8-8) and
low-voltage PECL (Positive ECL) outputs, operating off
the 3.3 V supply voltage.
The SSTL_3 and differential PECL output drivers drive
resistive terminations or transmission lines. At lower
clock frequencies, the SSTL_3 outputs can be
operated unterminated. See
Section 9, “Output
Termination”
1.15 Power-On Reset Detection (POR)
The ICS1523 has automatic POR circuitry, meaning it
resets itself if the supply voltage drops below a
threshold values of approximately 1.8 V. No external
connection to a reset signal is required.
1.9 Phase Frequency Detector (PFD)
The PFD compares the FUNC signal to the selected
input described below and controls the filter voltage by
enabling and disabling the charge pump. The charge
pump has programmable current drive and will source
and sink current as appropriate to keep the input and
the FUNC output aligned.
1.16 I
2
C Bus Serial Interface
The ICS1523 uses a 5 V tolerant, industry-standard
I
2
C-bus serial interface that runs at either low speed
(100 kHz) or high speed (400 kHz). The interface uses
12 indexed registers: one write-only, eight read/write,
and three read-only registers.
Two ICS1523 devices can be addressed according to
the state of the I2CADR pin. When this pin is low the
read address is 4Dh and the write address is 4Ch.
When the pin is high, the read address is 4Fh and the
write address is 4Eh. See
Section 11, “Programming”.
1.10 HSYNC and REF Inputs
One of the PFDs two possible inputs is HSYNC (pin 7).
HSYNC is conditioned by a high-performance
Schmitt-trigger. This preconditioned HSYNC signal,
called REF, is provided as a reference signal with a
short transition time. REF can be output on pin 14.
MDS ICS1523 ZC
3
Integrated Device Technology, Inc.
Tech Support: www.idt.com/go/clockhelp
Revision 020811
ICS1523
Video Clock Synthesizer with I
2
C Programmable Delay
Section 2
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin Descriptions
TYPE
POWER
POWER
IN/OUT
IN
IN
IN
IN
IN
IN
POWER
POWER
IN
IN
DESCRIPTION
Digital supply
Digital ground
Serial data
Serial clock
Charge pump enable
External feedback in
Horizontal sync
External filter
External filter return
Analog supply
Analog ground
Oscillator
I
2
C address
I
2
C-bus Data
I
2
C-bus Clock
Enables\Disables the charge pump
External feedback divider input
Clock input to PLL
External loop filter
External loop filter return
3.3 V for analog circuitry
Ground for analog circuitry
Input from oscillator or other high
frequency input
Chip I
2
C address select
Low = 4Dh read, 4Ch write
High = 4Fh read, 4Eh write
REF (Schmitt conditioned HSYNC) or
PLL lock output
Output selectable between a 4 clock
wide, active high HSYNC-like output,
and a Schmitt-trigger filtered HSYNC
Output driver for half speed clock
Output driver for full speed clock
3.3 V to output drivers
Ground for output drivers
PECL driver for full-speed clock
PECL driver for half-speed clock
Reference current for PECL outputs
1&2
1
1
1
1
1
COMMENTS
3.3 V to digital sections
Notes
PIN NAME
VDDD
VSSD
SDA
SCL
COAST
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
OSC
I
2
CADR
14
15
LOCK/REF
FUNC
SSTL
_
3 OUT
SSTL
_
3 OUT
Lock / Reference
Function output
16
17
18
19
20
21
22
23
24
CLK/2
CLK
VDDQ
VSSQ
CLK–
CLK+
CLK/2–
CLK/2+
IREF
SSTL
_
3 OUT
SSTL
_
3 OUT
POWER
POWER
OD OUT
OD OUT
IN
Pixel clock/2 output
Pixel clock output
Output driver supply
Output driver ground
Pixel clock outputs
Pixel clock/2 outputs
Reference current
Note 1: These LVTTL inputs are 5 V-tolerant.
Note 2: Connect to ground if unused.
MDS ICS1523 ZC
4
Integrated Device Technology, Inc.
Tech Support: www.idt.com/go/clockhelp
Revision 020811
ICS1523
Video Clock Synthesizer with I
2
C Programmable Delay
Section 3
Functional Block Diagram
MDS ICS1523 ZC
5
Integrated Device Technology, Inc.
Tech Support: www.idt.com/go/clockhelp
Revision 020811
(X) denotes pin number
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