(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
FEATURES
Frequency Range 10MHz to 220MHz
Zero input - output delay.
Low Output to Output Skew
Optional Drive Strength:
Standard (8mA)
PL123E-09
High (12mA)
PL123E-09H
2.5V or 3.3V, ±10% operation.
Available in 16-Pin SOP or TSSOP packages
DESCRIPTION
The PL123E-09 (-09H for High Drive) is a high perfor-
mance, low skew, low jitter zero delay buffer d esigned
to distribute high speed clocks. It has two low-skew
output banks, of 4 outputs each, that are synchronized
with the input. Control of the two banks o f outputs is
achieved by using the S1 and S2 inputs as shown in
the Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than
100ps,
the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM
REF
PLL
Mux
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
Bank A
REF
CLKA1
CLKA2
VDD
GND
CLKB1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Bank B
S1
S2
Selector
Inputs
CLKB2
CLKB3
CLKB4
CLKB2
S2
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 12/13/11 Page 1
(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
PIN DESCRIPTIONS
Name
REF
[1 ]
CLKA1
[2 ]
CLKA2
[2 ]
VDD
GND
CLKB1
[2 ]
CLKB2
[2 ]
S2
[3 ]
S1
[3 ]
CLKB3
[2 ]
CLKB4
[2 ]
CLKA3
[2 ]
CLKA4
[2 ]
CLKOUT
[2 ]
Package Type
TSSOP-16L
1
2
3
4,13
5,12
6
7
8
9
10
11
14
15
16
SOP-16L
1
2
3
4,13
5,12
6
7
8
9
10
11
14
15
16
Type
I
O
O
P
P
O
O
I
I
O
O
O
O
O
Description
Input reference frequency.
Buffered clock output, Bank A
Buffered clock output, Bank A
VDD connection
GND connection
Buffered clock output, Bank B
Buffered clock output, Bank B
Selector input
Selector input
Buffered clock output, Bank B
Buffered clock output, Bank B
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered clock output. Internal feedback on this pin.
Notes:
1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
(Bank A)
Three-state
Driven
Driven
Driven
CLOCK B1–B4
(Bank B)
Three-state
Three-state
Driven
Driven
CLKOUT
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
INPUT / OUTPUT SKEW CONTROL
The PL123E-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjust-
ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact Micrel for more information.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 12/13/11 Page 2
(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a pe rformance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency depend-
ant. Typical values to use are 0.1
F
for designs
using frequencies < 50MHz and 0.01F for designs
using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20
50 line
To CMOS Input
Connect a 33
series
resistor at each of the output
clocks to enhance the
stability of the output signal
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 12/13/11 Page 3
(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
ABSOLUTE M AXIM UM CONDITIONS
Supply Voltage to Ground Potenti al ...... –0.5V to 4.6V
DC Input Voltage ............................ V
SS
– 0.5V to 4.6V
Storage Temperature ..........................–65°C to 150°C
Junction Temperature ..................................... 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015)……………..> 2000V
OPERATING CONDITIONS
Description
Supply Voltage
Load Capacitance, <100 MHz, 3.3V
Load Capacitance, <100 MHz, 2.5V with High Drive
Load Capacitance, <133.3 MHz, 3.3V
Load Capacitance, <133.3 MHz, 2.5V with High Drive
Load Capacitance, <133.3 MHz, 2.5V with Standard Drive
Load Capacitance, >133.3 MHz, 3.3V
Load Capacitance, >133.3 MHz, 2.5V with High Drive
Input Capacitance
[5]
Closed-loop bandwidth (typical), 3.3V
Closed-loop bandwidth (typical), 2.5V
Output Impedance (typical), 3.3V High Drive
Output Impedance (typical), 3.3V Standard Drive
Output Impedance (typical), 2.5V High Drive
Output Impedance (typical), 2.5V Standard Drive
Power-up time for all V
DD
’s to reach minimum specified
voltage (power ramps must be monotonic)
Notes:
Parameter
V
DD
C
L [4 ]
Min
2.25
–
–
–
–
–
–
–
Max
3.63
30
30
22
22
15
15
15
5
1
0.5
23
33
26
39
Unit
V
pF
pF
pF
pF
pF
pF
pF
pF
MHz
MHz
Ω
Ω
Ω
Ω
C
IN
BW
R
OUT
–
t
PU
0.01
250
ms
4.
5.
6.
Applies to Test Circuit #1.
Applies to both REF Clock and internal feedback path on CLKOUT.
Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil -Spec 883E Method 1012.1.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 12/13/11 Page 4
(Preliminary)
PL123E-09
Max
3.63
0.8
V
DD
+ 0.3
±10
100
0.4
0.4
–
–
45
Unit
V
V
V
µA
µA
V
V
V
V
mA
Low Skew Zero Delay Buffer
3.3V DC ELECTRICAL SPECIFICATIONS
Description
Supply Voltage
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Supply Current
Parameter
V
DD
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
0 < V
IN
< V
IL
V
IN
= V
DD
I
OL
= 8 mA (Standard Drive)
I
OL
= 12 mA (High Drive)
I
OH
= –8 mA (Standard Drive)
I
OH
= –12 mA (High Drive)
Unloaded outputs, 66-MHz REF
Test Conditions
Min
2.97
–
2.5
–
–
–
–
2.4
2.4
–
2.5V
DC ELECTRICAL SPECIFICATIONS
Description
Supply Voltage
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Supply Current
Parameter
V
DD
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
0<V
IN
< V
IL
V
IN
= V
DD
I
OL
= 8 mA (Standard Drive)
I
OL
= 12 mA (High Drive)
I
OH
= –8 mA (Standard Drive)
I
OH
= –12 mA (High Drive)
Unloaded outputs, 66-MHz REF
Test Conditions
Min
2.25
–
1.7
–
–
–
–
V
DD
– 0.6
V
DD
– 0.6
–
Max
2.75
0.7
V
DD
+ 0.3
±10
100
0.5
0.5
–
–
30
Unit
V
V
V
µA
µA
V
V
mA
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 12/13/11 Page 5
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