74ALVCH16841
Rev. 3 — 12 September 2018
20-bit bus interface D-type latch; 3-state
Product data sheet
1. General description
The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch
and 3-state outputs for bus oriented applications. The two sections of each register are controlled
independently by the latch enable (nLE) and output enable (nOE) control gates.
When nOE is LOW, the data in the registers appears at the outputs. When nOE is HIGH the
outputs are in High-impedance OFF state. Operation of the nOE input does not affect the state of
the flip-flops.
The 74ALVCH16841 has active bus hold circuitry which is provided to hold unused or floating
data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down
resistors.
2. Features and benefits
•
•
•
•
•
•
•
•
•
•
Wide supply voltage range of 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Current drive ±24 mA at V
CC
= 3.0 V
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimize noise and ground bounce
All data inputs have bushold
Output drive capability 50 Ω transmission lines at 85 °C
3-state non-inverting outputs for bus oriented applications
Complies with JEDEC standards:
•
JESD8-5 (2.3 V to 2.7 V)
•
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
•
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
•
CDM JESD22-C101E exceeds 1000 V
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74ALVCH16841DGG −40 °C to +85 °C
TSSOP56
Description
Version
plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
Nexperia
74ALVCH16841
20-bit bus interface D-type latch; 3-state
4. Functional diagram
1OE
1
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
56
1LE
29
2LE
aaa-029040
2OE
28
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
1OE
1LE
2OE
2LE
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
1
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
EN2
C1
EN4
C3
1D
2
2
3
5
6
8
9
10
12
13
14
3D
4
15
16
17
19
20
21
23
24
26
27
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
aaa-029041
Fig. 1.
Logic symbol
1D0
D
Q
1Q0
2D0
Fig. 2.
D
IEC logic symbol
Q
2Q0
LATCH
1
LE
1LE
1OE
to 9 other channels
2LE
2OE
LATCH
11
LE
to 9 other channels
aaa-029042
Fig. 3.
Logic diagram
VCC
data
input
to internal circuit
mna004
Fig. 4.
Bushold circuit
74ALVCH16841
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 12 September 2018
2 / 12
Nexperia
74ALVCH16841
20-bit bus interface D-type latch; 3-state
5. Pinning information
5.1. Pinning
74ALVCH16841
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
56 1LE
55 1D0
54 1D1
53 GND
52 1D2
51 1D3
50 V
CC
49 1D4
48 1D5
47 1D6
46 GND
45 1D7
44 1D8
43 1D9
42 2D0
41 2D1
40 2D2
39 GND
38 2D3
37 2D4
36 2D5
35 V
CC
34 2D6
33 2D7
32 GND
31 2D8
30 2D9
29 2LE
aaa-029043
1Q6 10
GND 11
1Q7 12
1Q8 13
1Q9 14
2Q0 15
2Q1 16
2Q2 17
GND 18
2Q3 19
2Q4 20
2Q5 21
V
CC
22
2Q6 23
2Q7 24
GND 25
2Q8 26
2Q9 27
2OE 28
Fig. 5.
Pin configuration SOT364-1 (TSSOP56)
5.2. Pin description
Table 2. Pin description
Symbol
1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7, 1D8, 1D9
2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7, 2D8, 2D9
1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7, 1Q8, 1Q9
2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7, 2Q8, 2Q9
1OE, 2OE
1LE, 2LE
GND
V
CC
Pin
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1, 28
56, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
Description
data input
data input
data output
data output
output enable inputs
(active-LOW)
latch enable inputs
ground (0 V)
supply voltage
74ALVCH16841
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 12 September 2018
3 / 12
Nexperia
74ALVCH16841
20-bit bus interface D-type latch; 3-state
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Inputs
nOE
L
L
L
H
nLE
H
H
L
X
nDn
L
H
X
X
Outputs
nQn
L
H
Q
0
Z
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
For control pins
For data inputs
V
I
< 0 V
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
[1]
[1]
[1]
Min
-0.5
-0.5
-0.5
-0.5
-50
-
-
-
-100
-65
Max
+4.6
+4.6
V
CC
+ 0.5
V
CC
+ 0.5
-
±50
±50
100
-
+150
600
Unit
V
V
V
V
mA
mA
mA
mA
mA
°C
mW
T
amb
= -40 °C to +85 °C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Above 55 °C the value of P
tot
derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
in free air
V
CC
= 3.0 V to 3.6 V
input transition rise and fall rate V
CC
= 2.3 V to 3.0 V
for maximum speed performance; 30 pF output load
for maximum speed performance; 50 pF output load
Min
2.3
3.0
0
0
-40
-
-
Max
2.7
3.6
V
CC
V
CC
+85
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
74ALVCH16841
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 12 September 2018
4 / 12
Nexperia
74ALVCH16841
20-bit bus interface D-type latch; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). T
amb
= -40 °C to +85 °C
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
Conditions
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
I
= V
IH
or V
IL
I
O
= -100 μA; V
CC
= 2.3 V to 3.6 V
I
O
= -6 mA; V
CC
= 2.3 V
I
O
= -12 mA; V
CC
= 2.3 V
I
O
= -12 mA; V
CC
= 2.7 V
I
O
= -12 mA; V
CC
= 3.0 V
I
O
= -24 mA; V
CC
= 3.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 100 μA; V
CC
= 2.3 V to 3.6 V
I
O
= 6 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
I
OZ
I
CC
ΔI
CC
I
BHL
I
BHH
I
BHLO
I
BHHO
C
I
[1]
Min
1.7
2.0
-
-
V
CC
- 0.2
V
CC
- 0.3
V
CC
- 0.6
V
CC
- 0.5
V
CC
- 0.6
V
CC
- 1.0
-
-
-
-
-
-
-
-
-
45
75
-45
-75
500
-500
-
Typ[1]
1.2
1.5
1.2
1.5
V
CC
V
CC
- 0.08
V
CC
- 0.26
V
CC
- 0.14
V
CC
- 0.09
V
CC
- 0.28
GND
0.07
0.15
0.14
0.27
0.1
0.1
0.2
150
-
150
-
-175
-
-
5.0
Max
-
-
0.7
0.8
-
-
-
-
-
-
0.20
0.40
0.70
0.40
0.55
5
10
40
750
-
-
-
-
-
-
-
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
pF
input
leakage current
OFF-state
output current
supply current
additional
supply current
bus hold LOW
current
bus hold HIGH
current
bus hold LOW
overdrive current
bus hold HIGH
overdrive current
input capacitance
V
CC
= 2.3 V to 3.6 V; V
I
= V
CC
or GND
V
CC
= 2.3 V to 3.6 V; V
I
= V
IH
or V
IL
;
V
O
= V
CC
or GND
V
CC
= 2.3 V to 3.6 V; V
I
= V
CC
or GND;
I
O
= 0 A
V
CC
= 2.3 V to 3.6 V; V
I
= V
CC
- 0.6 V;
I
O
= 0 A
V
CC
= 2.3 V; V
I
= 0.7 V
V
CC
= 3.0 V; V
I
= 0.8 V
V
CC
= 2.3 V; V
I
= 1.7 V
V
CC
= 3.0 V; V
I
= 2.0 V
V
CC
= 3.6 V
V
CC
= 3.6 V
All typical values are measured at T
amb
= 25 °C.
74ALVCH16841
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 12 September 2018
5 / 12
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