FeaTures
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LTC3335
Nanopower Buck-Boost
DC/DC with Integrated
Coulomb Counter
DescripTion
The
LTC
®
3335
is a high efficiency, low quiescent current
(680nA) buck-boost DC/DC converter with an integrated
precision coulomb counter which monitors accumulated
battery discharge in long life battery powered applications.
The buck-boost can operate down to 1.8V on its input and
provides eight pin-selectable output voltages with up to
50mA of output current.
The coulomb counter stores the accumulated battery dis-
charge in an internal register accessible via an I
2
C interface.
The LTC3335 features a programmable discharge alarm
threshold. When the threshold is reached, an interrupt is
generated at the
IRQ
pin.
To accommodate a wide range of battery types and sizes,
the peak input current can be selected from as low as 5mA
to as high as 250mA and the full-scale coulomb counter
has a programmable range of 32,768:1.
The LTC3335 is available in a 3mm
×
4mm QFN-20 package.
L,
LT, LTC, LTM, Linear Technology, the Linear logo, SmartMesh and Dust Networks are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
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680nA Input Quiescent Current (Output in
Regulation at No Load)
1.8V to 5.5V Input Operating Range
Selectable Output Voltages of 1.8V, 2.5V, 2.8V,
3V, 3.3V, 3.6V, 4.5V, 5V
Integrated Coulomb Counter Measures
Accumulated Battery Discharge
±5% Battery Discharge Measurement Accuracy
Programmable Peak Input Current of 5mA, 10mA,
15mA, 25mA, 50mA, 100mA, 150mA, 250mA
Up to 50mA of Output Current
Up to 90% Efficiency
Programmable Coulomb Counter Prescaler for Wide
Range of Battery Sizes
Programmable Discharge Alarm Threshold
I
2
C Interface
Low Profile (0.75mm) 20-Lead (3mm
×
4mm) QFN
Package
applicaTions
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Long Lifetime Primary Cell Battery Applications
Wireless Sensors
Remote Monitors
Dust Networks
®
SmartMesh
®
Applications
Typical applicaTion
2.2mH TO 47µH
100
I
PEAK
= 5mA TO 250mA
PRIMARY CELL
SW1
BAT
10µF
PBAT
EN
DV
CC
10k
I
2
C
3
3
10k
SCL
SDA
IPK[2:0]
OUT[2:0]
GND
3335 TA01
Efficiency vs Load for 100mA
I
PEAK
Setting
90
1.8V TO 5V
47µF
EFFICIENCY (%)
80
70
60
50
40
30
20 BAT = 3.6V
L = 150µH
10
DCR = 0.3
0
0.001
0.01
V
OUT
= 1.8V
V
OUT
= 2.5V
V
OUT
= 3.3V
V
OUT
= 5V
1
0.1
I
LOAD
(mA)
10
100
3335 TA01a
SW2
V
OUT
PV
OUT
+
LTC3335
IRQ
PGOOD
For more information
www.linear.com/LTC3335
1
3335f
LTC3335
absoluTe MaxiMuM raTings
(Note 1)
pin conFiguraTion
TOP VIEW
PGOOD
GNDA
16 EN
15 IPK2
21
PGND
14 IPK1
13 IPK0
12 V
OUT
11 PV
OUT
7
BAT
8
PBAT
9 10
SW1
SW2
SCL
SDA
DV
CC
OUT2
OUT1
OUT0
GNDD
1
2
3
4
5
6
IRQ
BAT, PBAT, V
OUT
, PV
OUT
Voltage .................. –0.3V to 6V
EN, OUT[2:0],
IPK[2:0] Voltage .....–0.3V to [Lesser of (BAT + 0.3V) or 6V]
DV
CC
, SDA, SCL Voltage .............................. –0.3V to 6V
PGOOD,
IRQ
Voltage .....–0.3V to [Lesser of (DV
CC
+ 0.3V) or 6V]
SW1, SW2 Current .............................................. 350mA
Operating Junction Temperature Range
(Notes 2, 3) ............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
20 19 18 17
UDC PACKAGE
20-LEAD (3mm
×
4mm) PLASTIC QFN
T
JMAX
= 125°C,
θ
JA
= 52°C/W
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC3335EUDC#PBF
LTC3335IUDC#PBF
TAPE AND REEL
LTC3335EUDC#TRPBF
LTC3335IUDC#TRPBF
PART MARKING
LGTR
LGTR
PACKAGE DESCRIPTION
20-Lead (3mm × 4mm) Plastic QFN
20-Lead (3mm × 4mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
2
3335f
For more information
www.linear.com/LTC3335
LTC3335
elecTrical characTerisTics
PARAMETER
Buck-Boost DC/DC
Input Voltage Range
Input Quiescent Current
Shutdown
Sleeping (In Regulation)
Not Sleeping
Regulated Output Voltage
BAT and PBAT Combined
EN = 0
EN = 1
EN = 1, I
SW1
= I
SW2
= 0 (Note 4)
1.8V Output Setting
Sleep Threshold
Wake-Up Threshold
2.5V Output Setting
Sleep Threshold
Wake-Up Threshold
2.8V Output Setting
Sleep Threshold
Wake-Up Threshold
3V Output Setting
Sleep Threshold
Wake-Up Threshold
3.3V Output Setting
Sleep Threshold
Wake-Up Threshold
3.6V Output Setting
Sleep Threshold
Wake-Up Threshold
4.5V Output Setting
Sleep Threshold
Wake-Up Threshold
5V Output Setting
Sleep Threshold
Wake-Up Threshold
PGOOD Falling Threshold
V
OUT
Leakage Current
Input Peak Switch Current
(Note 5)
All Output Settings, V
OUT
in Regulation
250mA I
PEAK
Setting (Note 6)
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
The
l
denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at T
A
= 25°C (Note 2). BAT = PBAT = DV
CC
= 3.6V, GNDA = GNDD = PGND = 0V, V
OUT
= PV
OUT
.
CONDITIONS
MIN
1.8
440
680
360
1.806
1.794
2.508
2.492
2.809
2.791
3.010
2.990
3.311
3.289
3.612
3.588
4.515
4.485
5.017
4.983
92
100
225
200
135
125
90
85
45
42.5
21.5
20
12.5
12
8.25
8
4
3.75
20
250
250
150
150
100
100
50
50
25
25
15
15
10
10
5
5
0
TYP
MAX
5.5
700
1000
540
1.863
UNITS
V
nA
nA
µA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
%
nA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3335f
1.737
2.425
2.575
2.716
2.884
2.910
3.090
3.200
3.400
3.492
3.708
4.365
4.635
4.850
89
5.150
95
150
275
275
165
165
110
110
55
55
27.5
27.5
16.5
16.5
11
11
5.5
5.5
150mA I
PEAK
Setting (Note 6)
l
100mA I
PEAK
Setting (Note 6)
l
50mA I
PEAK
Setting (Note 6)
l
25mA I
PEAK
Setting (Note 6)
l
15mA I
PEAK
Setting (Note 6)
l
10mA I
PEAK
Setting (Note 6)
l
5mA I
PEAK
Setting (Note 6)
l
I
ZERO
Current Threshold (Note 7)
Available Output Current
All I
PEAK
Settings
100mA I
PEAK
Setting, V
OUT
= 3.3V
For more information
www.linear.com/LTC3335
3
LTC3335
elecTrical characTerisTics
PARAMETER
PMOS Switch A On-Resistance
(From PBAT to SW1)
CONDITIONS
250mA I
PEAK
Setting
150mA I
PEAK
Setting
100mA I
PEAK
Setting
50mA I
PEAK
Setting
25mA I
PEAK
Setting
15mA I
PEAK
Setting
10mA I
PEAK
Setting
5mA I
PEAK
Setting
250mA I
PEAK
Setting
150mA I
PEAK
Setting
100mA I
PEAK
Setting
50mA I
PEAK
Setting
25mA I
PEAK
Setting
15mA I
PEAK
Setting
10mA I
PEAK
Setting
5mA I
PEAK
Setting
IPK[2:0] = 1xx
IPK[2:0] = 0xx
250mA I
PEAK
Setting
150mA I
PEAK
Setting
100mA I
PEAK
Setting
50mA I
PEAK
Setting
25mA I
PEAK
Setting
15mA I
PEAK
Setting
10mA I
PEAK
Setting
5mA I
PEAK
Setting
Switches A, D
SW1 = SW2 = 0V, BAT = 5.5V, V
OUT
= 5.5V
Switches B, C
SW1 = BAT = 5.5V, SW2 = V
OUT
= 5.5V
250mA I
PEAK
Setting
150mA I
PEAK
Setting
100mA I
PEAK
Setting (Note 10)
50mA I
PEAK
Setting
25mA I
PEAK
Setting
15mA I
PEAK
Setting
10mA I
PEAK
Setting
5mA I
PEAK
Setting
l
The
l
denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at T
A
= 25°C (Note 2). BAT = PBAT = DV
CC
= 3.6V, GNDA = GNDD = PGND = 0V, V
OUT
= PV
OUT
.
MIN
TYP
0.38
0.55
0.76
1.40
2.67
4.36
6.48
12.82
0.57
0.85
1.20
2.26
4.37
7.18
10.69
21.20
0.37
2.05
0.60
0.86
1.18
2.14
4.06
6.61
9.81
19.40
0
0
10
10
MAX
UNITS
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
nA
nA
NMOS Switch B On-Resistance
(From SW1 to PGND)
NMOS Switch C On-Resistance
(From SW2 to PGND)
PMOS Switch D On-Resistance
(From PV
OUT
to SW2)
PV
OUT
= V
OUT
= 3.3V
PMOS Switch Leakage
NMOS Switch Leakage
Coulomb Counter
q
LSB
(for Prescaler setting M=0)
(Notes 8,9)
7.031
4.218
2.728
2.812
1.406
703.1
421.8
281.2
140.6
1.094
l
A
•
hr
A
•
hr
2.896
A
•
hr
A
•
hr
mA
•
hr
mA
•
hr
mA
•
hr
mA
•
hr
mA
•
hr
2.885
5
A
•
hr
A
•
hr
%
Full-Scale Coulomb Count
(Battery Capacity)
Total Unadjusted Coulomb Counter
Error
(Note 10)
Digital Inputs and Output
DV
CC
Voltage
Digital Input High Voltage
5mA I
PEAK
Setting, M=15, L = 2.2mH; (Smallest Battery)
100mA I
PEAK
Setting, M = 8, L = 100μH
250mA I
PEAK
Setting, M = 0, L = 47μH; (Largest Battery)
Buck-Boost Switching, 100mA I
PEAK
Setting, V
OUT
= 3.3V, BAT = 3.6V
l
–5
2.717
2.801
1793
l
1.8
BAT – 0.5
70
5.5
V
%DV
CC
V
For Pins EN, IPK[2:0], OUT[2:0]
For Pins SDA, SCL
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3335f
For more information
www.linear.com/LTC3335
LTC3335
elecTrical characTerisTics
PARAMETER
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Input High Current
Input Low Current
I
2
C Read Address
I
2
C Write Address
Clock Operating Frequency
Bus Free Time Between
STOP/START
Repeated START Set-Up Time
Hold Time (Repeated) START
Condition
Set-Up Time for STOP Condition
Data Set-Up Time (Input)
Data Hold Time (Input)
Data Hold Time (Output)
Clock/Data Fall Time
Clock/Data Rise Time
Clock LOW Period
Clock HIGH Period
Spike Suppression Time
f
SCL
t
BUF
t
SU,STA
t
HD,STA
t
SU,STO
t
SU,DAT
t
HD,DATI
t
HD,DATO
t
f
t
r
t
LOW
t
HIGH
t
SP
1.3
600
600
600
100
0
0
20
20
1.3
0.6
50
0.9
300
300
CONDITIONS
For Pins EN, IPK[2:0], OUT[2:0]
For Pins SDA, SCL
For Pins PGOOD,
IRQ;
1µA Out of Pin
For Pins PGOOD,
IRQ;
1µA Into Pin
For Pin SDA; 3mA Into Pin
For Pins EN, IPK[2:0], OUT[2:0], SDA, SCL
For Pins EN, IPK[2:0], OUT[2:0], SDA, SCL
l
l
DV
CC
– 0.5
l
The
l
denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at T
A
= 25°C (Note 2). BAT = PBAT = DV
CC
= 3.6V, GNDA = GNDD = PGND = 0V, V
OUT
= PV
OUT
.
MIN
TYP
MAX
0.5
30
0.5
0.4
0
0
11001001
11001000
400
kHz
µs
ns
ns
ns
ns
µs
µs
ns
ns
µs
µs
ns
10
10
UNITS
V
%DV
CC
V
V
V
nA
nA
I
2
C Timing Characteristics (See Figure 1)
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
The LTC3335 is tested under pulsed load conditions such that T
J
≈
T
A
. The LTC3335E is guaranteed to meet specifications from 0°C to 85°C.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization, and correlation with statistical
process controls. The LTC3335I is guaranteed over the –40°C to 125°C
operating junction temperature range. Note that the maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal impedance, and other environmental factors.
Note 3:
T
J
is calculated from the ambient T
A
and power dissipation P
D
according to the following formula: T
J
= T
A
+ (P
D
•
θ
JA
).
Note 4:
Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5:
The PGOOD Falling Threshold is specified as a percentage of the
average of the measured sleep and wake-up thresholds for each selected
output. The PGOOD rising threshold is equal to the sleep threshold. See
Regulated Output Voltage specification.
Note 6:
For the 100mA I
PEAK
setting, the value given in the table is
measured in a closed-loop set-up with a 100µH inductor, a 3.6V BAT
voltage, and the LTC3335 switching. For the other seven I
PEAK
settings,
the values given in the table are calculated from an open-loop DC
measurement of I
PEAK
(LTC3335 not switching), the propagation delay of
the I
PEAK
comparator, and the recommended inductor value for each I
PEAK
setting.
Note 7:
I
ZERO
measurements are performed when the LTC3335 is not
switching. The values seen in operation will be slightly lower due to the
propagation delay of the comparators
Note 8:
The equivalent charge of an LSB in the accumulated charge
register depends on the I
PEAK
setting and the internal pre-scaling factor M.
See Choosing Coulomb Counter Prescaler M section for more information.
1mA
•
hr = 3.6A
•
s = 3.6C.
Note 9:
The values given in the table are for applications using the
recommended inductor value for each I
PEAK
setting.
Note 10:
The specified accuracy of q
LSB
in percent is better than that of
the corresponding I
PEAK
because the full-scale ON time of the AC(ON)
time measurement is internally adjusted to compensate for errors in the
actual I
PEAK
value. The Total Unadjusted Coulomb Counter Error specified
includes any inaccuracy in q
LSB
.
For more information
www.linear.com/LTC3335
5
3335f
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