Data Sheet, Rev 1.
August 2001
NetLight
®
1430G5 Type SONET/SDH
Long-Reach Transceivers with Clock Recovery
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Wide dynamic range receiver with InGaAs PIN
photodetector
LVTTL signal-detect output
Low power dissipation
Raised ECL (LVPECL) logic data interfaces
Operating case temperature range: –40
°C
to
+85
°C
Agere Systems Inc. Reliability and Qualification
Program for built-in quality and reliability
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Available in a small form factor, plastic package, the
1430G5 are high-performance, cost-effective transceivers for
SONET/SDH long-reach applications at 155 Mbits/s.
Description
The 1430G5-Type transceiver is a high-speed, cost-
effective optical transceiver that is compliant with the
International Telecommunication Union Telecommu-
nication (ITU-T) G.957 specifications for use in
SONET and SDH long-reach applications. The
1430G5 operates at the OC-3/STM-1 rate of
155 Mbits/s. The transceiver features Agere Sys-
tems’ optics and is packaged in a narrow-width plas-
tic housing with two 1 meter fiber pigtails terminated
with LC connectors. The 20-pin package and pinout
conform to a multisource transceiver agreement.
The transmitter features differential LVPECL logic
level data inputs, a LVTTL logic level disable input.
The receiver features differential LVPECL logic level
data and clock outputs, and a LVTTL logic level
signal-detect output.
Features
s
SONET LR-1/SDH L1.1 Compliant (ITU-T G.957
Specifications)
Small form factor, RJ-45 size, multisourced 20-pin
package
Requires single 3.3 V power supply
Clock recovery
Fiber pigtail
Uncooled 1300 nm laser transmitter with automatic
output power control
Transmitter disable input
Analog alarm outputs
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NetLight
1430G5 Type SONET/SDH
Long-Reach Transceivers with Clock Recovery
Data Sheet, Rev 1.
August 2001
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
Supply Voltage
Operating Case Temperature Range
Storage Case Temperature Range
Lead Soldering Temperature/Time
Operating Wavelength Range
Symbol
V
CC
T
C
T
stg
—
λ
Min
0
–40
–40
—
1.1
Max
3.6
85
85
250/10
1.6
Unit
V
°C
°C
°C/s
nm
Pin Information
TX
20 19 18 17 16 15 14 13 12 11
20-PIN MODULE - TOP VIEW
RX
1 2 3 4 5 6 7 8 9 10
1-967(F).b
Figure 1. 1430G5 and 1430H5-Type Transceivers, 20-Pin Configuration, Top View
Table 1. Transceiver Pin Descriptions
Pin
Number
MS
Symbol
Name/Description
Receiver
Mounting Studs.
The mounting studs are provided for transceiver mechani-
cal attachment to the circuit board. They may also provide an optional con-
nection of the transceiver to the equipment chassis ground.
Photodetector Bias.
This lead supplies bias for the PIN photodetector diode.
Logic
Family
NA
MS
1
2
3
4
5
6
7
8
9
10
Photode-
tector Bias
Receiver Signal Ground.
V
EER
Receiver Signal Ground.
V
EER
Received Recovered
Clock
Out.
The rising edge occurs at the rising edge of
CLK–
the received data output. The falling edge occurs in the middle of the received
data bit period.
Received Recovered Clock Out.
The falling edge occurs at the rising edge
CLK+
of the received data output. The rising edge occurs in the middle of the
received data bit period.
Receiver Signal Ground.
V
EER
Receiver Power Supply.
V
CCR
Signal Detect.
SD
Normal operation: logic one output.
Fault condition: logic zero output.
Received
DATA
Out.
No Internal terminations will be provided.
RD–
Received DATA Out.
No internal terminations will be provided.
RD+
NA
NA
NA
LVPECL
LVPECL
NA
NA
LVTTL
LVPECL
LVPECL
2
Agere Systems Inc.
Data Sheet, Rev 1.
August 2001
NetLight
1430G5 Type SONET/SDH
Long-Reach Transceivers with Clock Recovery
Pin Information
(continued)
Table 1. Transceiver Pin Descriptions
(continued)
Pin
Number
11
12
13
14
15
16
17
Symbol
Name/Description
Logic
Family
V
CCT
V
EET
T
DIS
TD+
TD–
V
EET
Bmon–
18
19
B
MON
+
P
MON
–
20
P
MON
+
Transmitter
Transmitter Power Supply.
NA
Transmitter Signal Ground.
NA
Transmitter Disable.
LVTTL
Transmitter DATA In.
LVPECL
Transmitter DATA In Bar.
LVPECL
Transmitter Signal Ground.
NA
Laser Diode Bias Current Monitor—Negative End.
The laser bias current
NA
is accessible as a dc-voltage by measuring the voltage developed across pins
17 and 18.
Laser Diode Bias Current Monitor—Positive End.
See pin 17 description.
NA
Laser Diode Optical Power Monitor—Negative End.
The back-facet diode
NA
monitor current is accessible as a dc-voltage by measuring the voltage devel-
oped across pins 19 and 20.
Laser Diode Optical Power Monitor—Positive End.
See pin 19 description.
NA
Electrostatic Discharge
Caution: This device is susceptible to damage as
a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow
EIA
®
Stan-
dard
EIA-625.
Although protection circuitry is designed into the
device, take proper precautions to avoid exposure to
ESD.
Agere Systems employs a human-body model (HBM)
for ESD-susceptibility testing and protection-design
evaluation. ESD voltage thresholds are dependent on
the critical parameters used to define the model. A
standard HBM (resistance = 1.5 kΩ, capacitance =
100 pF) is widely used and, therefore, can be used for
comparison purposes. The HBM ESD threshold estab-
lished for the 1430G5 transceiver is
±1000
V.
Printed-Wiring Board Layout Considerations
A fiber-optic receiver employs a very high gain, wide
bandwidth transimpedance amplifier. This amplifier
detects and amplifies signals that are only tens of nA in
amplitude when the receiver is operating near its sensi-
tivity limit. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver's sensitivity and can also degrade the perfor-
mance of the receiver's signal detect (SD) circuit. To
minimize the coupling of unwanted noise into the
receiver, careful attention must be given to the printed-
wiring board.
At a minimum, a double-sided printed-wiring board
(PWB) with a large component-side ground plane
beneath the transceiver must be used. In applications
that include many other high-speed devices, a multi-
layer PWB is highly recommended. This permits the
placement of power and ground on separate layers,
which allows them to be isolated from the signal lines.
Multilayer construction also permits the routing of sen-
sitive signal traces away from high-level, high-speed
signal lines. To minimize the possibility of coupling
noise into the receiver section, high-level, high-speed
signals such as transmitter inputs and clock lines
should be routed as far away as possible from the
receiver pins.
Application Information
The 1430 receiver section is a highly sensitive fiber-
optic receiver. Although the data outputs are digital
logic levels (LVPECL), the device should be thought of
as an analog component. When laying out system
application boards, the 1430 transceiver should receive
the same type of consideration one would give to a
sensitive analog component.
Agere Systems Inc.
3
NetLight
1430G5 Type SONET/SDH
Long-Reach Transceivers with Clock Recovery
Data Sheet, Rev 1.
August 2001
Application Information
(continued)
Noise that couples into the receiver through the power
supply pins can also degrade performance. It is
recommended that the pi filter, shown in Figure 3, be
used for both the transmitter and receiver power
supplies.
its performance. Excessive ringing due to reflections
caused by improperly terminated signal lines makes it
difficult for the component receiving these signals to
decipher the proper logic levels and can cause transi-
tions to occur where none were intended. Also, by min-
imizing high-frequency ringing, possible EMI problems
can be avoided.
The signal-detect output is LVTTL logic. A logic low at
this output indicates that the optical signal into the
receiver has been interrupted or that the light level has
fallen below the minimum signal detect threshold. This
output should not be used as an error rate indicator,
since its switching threshold is determined only by the
magnitude of the incoming optical signal.
Data, Clock, and Signal Detect Outputs
The data, clock, and signal detect outputs of the 1430
transceiver are driven by open-emitter NPN transistors,
which have an output impedance of approximately 7
Ω.
Each output can provide approximately 50 mA maxi-
mum current to a 50
Ω
load terminated to V
CC
– 2.0 V.
Due to the high switching speeds of ECL outputs,
transmission line design must be used to interconnect
components. To ensure optimum signal fidelity, both
data outputs (RD+/RD–) and clock outputs
(CLK+/CLK–) should be terminated identically. The sig-
nal lines connecting the data clock outputs to the next
device should be equal in length and have matched
impedances. Controlled impedance stripline or micro-
strip construction must be used to preserve the quality
of the signal into the next component and to minimize
reflections back into the receiver, which could degrade
Transceiver Processing
The transceiver and plug can withstand normal wave
soldering and aqueous spray cleaning processes.
However, the transceiver is not hermetic, and should
not be subjected to immersion in cleaning solvents.
The transceiver case should not be exposed to temper-
atures in excess of 125
°C.
The fiber pigtail cannot
exceed 85
°C.
The transceiver pins can be wave sol-
dered at 250
°C
for up to 10 seconds.
Transceiver Optical and Electrical Characteristics
Table 2
.
Transmitter Optical and Electrical Characteristics
(T
C
= –40
°C
to +85
°C;
V
CC
= 3.135 V—3.465 V)
Parameter
Average Optical Output Power L-1.1
Optical Wavelength L-1.1
Spectral Width
Side-mode Suppression Ratio
Dynamic Extinction Ratio
Power Supply Current
Input Data Voltage:
Low
High
Transmit Disable Voltage
Transmit Enable Voltage
Laser Bias Voltage
Laser Back-facet Monitor Voltage
Symbol
P
O
λ
C
∆λ
20
SMSR
EXT
I
CCT
V
IL
V
IH
V
D
V
EN
V
BIAS
V
BF
Min
–5.0
1280
—
30
10
—
Max
0
1335
1
—
—
200
Unit
dBm
nm
nm
dB
dB
mA
V
V
V
V
V
V
V
CC
– 1.810 V
CC
– 1.475
V
CC
– 1.165 V
CC
– 0.880
V
CC
– 1.165
V
EE
0
0.01
V
CC
V
EE
+ 0.8
0.70
0.20
4
Agere Systems Inc.
Data Sheet, Rev 1.
August 2001
NetLight
1430G5 Type SONET/SDH
Long-Reach Transceivers with Clock Recovery
Application Information
(continued)
Table 3. Receiver Optical and Electrical Characteristics
(T
C
= –40
°C
to +85
°C;
V
CC
= 3.135 V—3.465 V)
Parameter
Average Sensitivity:
*
L-1.1
Maximum Input Power L-1.1
*
Link Status Switching Threshold:
Decreasing Light L-1.1
Increasing Light L-1.1
Link Status Hysteresis
Power Supply Current
Output Data Voltage/Clock Voltage:
Low
High
Signal Detect Output Voltage:
Low
High
Clock Duty Cycle
Output Clock Random Jitter
Output Clock Random Jitter Peaking
Clock/Data Alignment L-1.1 (See Figure 2.)
Jitter Tolerance/Jitter Transfer
* For 1 x 10
–10
BER with an optical input using 2
23
– 1 PRBS.
Symbol
P
I
P
MAX
LST
D
LST
I
HYS
I
CCR
V
OL
V
OH
V
OL
V
OH
DC
J
C
J
P
TCDA
Min
—
–10
–45
—
0.5
—
V
CC
– 1.86
V
CC
– 1.025
0.0
2.4
45
—
—
–0.8
Max
–34
—
–35
–34.5
6.0
200
V
CC
– 1.50
V
CC
– 0.88
0.8
V
CC
55
0.01
0.1
0.8
Unit
dBm
dBm
dBm
dBm
dB
mA
V
V
V
V
%
UI
dB
ns
Telcordia Technologies™
GR-253-CORE and
ITU-TG.958 Compliant
DATA
OUT
50%
CLOCK
OUT
50%
T
CDA
1-725(F).b
Figure 2. Clock/Data Alignment
Agere Systems Inc.
5
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