Preliminary
FM25LX64
64Kb Serial 1.5V F-RAM Memory
FEATURES
64K bit Ferroelectric Nonvolatile RAM
Organized as 8,192 x 8 bits
High Endurance 1 Trillion (10
12
) Read/Writes
36 Year Data Retention at +75ºC
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Fast SPI Interface
Up to 20 MHz Frequency
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Software Write-Protection (BP bits)
Hardware Write-Protect (/WP pin)
Active-Low RESET Input
Holds Device in Reset State While Power
Stabilizes
Reduces Time to First F-RAM Access
Allows Freedom of Power Supply Ramp Rates
Low Voltage/ Low Energy Consumption
Low Voltage Operation 1.5V +0.15V, -0.1V
20
A
(typ.) Active Current at 1 MHz
0.1
A
(typ.) Standby Current
Industry Standard Configuration
Industrial Temperature -40C to +85C
8-pin “Green”/RoHS SOIC Package
DESCRIPTION
The FM25LX64 is a 1.5V 64-kilobit nonvolatile
memory employing an advanced ferroelectric
process. A ferroelectric random access memory or F-
RAM is nonvolatile and performs reads and writes
like a RAM. It provides reliable data retention for 36
years while eliminating the complexities, overhead,
and system level reliability problems caused by
EEPROM and other nonvolatile memories.
The FM25LX64 performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array immediately after each byte has
been successfully transferred to the device. The next
bus cycle may commence immediately without the
need for data polling. In addition, the product offers
substantial write endurance compared with other
nonvolatile memories. The FM25LX64 is capable of
supporting 10
12
read/write cycles, or 1 million times
more write cycles than EEPROM.
These capabilities make the FM25LX64 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
The FM25LX64 provides substantial benefits to users
of serial EEPROM as a hardware drop-in
replacement. The FM25LX64 uses the high-speed
SPI bus, which enhances the high-speed write
capability
of
F-RAM
technology.
Device
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
PIN CONFIGURATION
CS
SO
WP
VSS
Pin Name
/CS
SCK
SI
SO
/RST
/WP
VDD
VSS
1
2
3
4
8
7
6
5
VDD
RST
SCK
SI
Function
Chip Select
Serial Clock
Serial Data Input
Serial Data Output
Reset Input
Write Protect Input
Supply Voltage
Ground
Ordering Information
FM25LX64-G
“Green” 8-pin SOIC
FM25LX64-GTR
“Green” 8-pin SOIC,
Tape & Reel
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Rev. 1.1
Feb. 2012
Page 1 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
RST
CS
SCK
Instruction Decode
Clock Generator
Control Logic
Write Protect
1,024 x 64
FRAM Array
Instruction Register
Address Register
Counter
SI
13
8
Data I/O Register
3
Nonvolatile Status
Register
SO
Figure 1. Block Diagram
PIN DESCRIPTIONS
Pin Name
/RST
I/O
Input
Description
Reset Input: This active-low pin is used to hold the memory in a reset state while
power is being stabilized. When /RST is low, the interface is inactive and the SPI state
machine is reset. Once Vdd is within spec, the /RST pin may be driven high. The
memory is ready for commands within t
PU
.
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode and ignores other inputs. When low, the device internally
activates the SCK signal. A falling edge on /CS must occur prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the rising edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet I
DD
specifications.
Serial Output: This is the data output pin. It behaves differently from a standard SPI
SO pin. Data is driven during a read from the rising edge of SCK instead of the falling
edge. SO is driven at all times.
Write Protect: This active low pin prevents write operations to the status register only.
A complete explanation of write protection is provided on pages 7 and 8.
Power Supply (1.4V to 1.65V)
Ground
/CS
Input
SCK
Input
SI
Input
SO
Output
/WP
VDD
VSS
Input
Supply
Supply
Rev. 1.1
Feb. 2012
Page 2 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
OVERVIEW
The FM25LX64 is a 1.5V serial F-RAM memory. The memory array is logically organized as 8,192 x 8 and is
accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the F-RAM is
similar to serial EEPROMs. The major difference between the FM25LX64 and a serial EEPROM with the same
pinout is the F-RAM’s superior write performance.
MEMORY ARCHITECTURE
When accessing the FM25LX64, the user addresses 8,192 locations of 8 data bits each. These data bits are
shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select, an op-code, and
a two-byte address. The upper 3 bits of the address range are ‘don’t care’ values. The complete address of 13-bits
specifies each byte address uniquely.
Most functions of the FM25LX64 either are controlled by the SPI interface or are handled automatically by on-
board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial
protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus
transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in
the interface section.
Users expect several obvious system benefits from the FM25LX64 due to its fast write cycle and high endurance
as compared to EEPROM. In applications that have a limited power budget, the fast-write and low-power
operation provides a much lower energy solution for nonvolatile store compared to EEPROM since the access is
completed quicker and at a very low voltage. By contrast, an EEPROM requires milliseconds to perform a write
operation and at much higher currents.
RESET
A reset input (/RST) is provided as a means to hold the memory interface in a reset state during power cycle
events. When /RST is driven low, the memory enters a reset condition. In this state, the interface is locked out
and the SO pin is high impedance. When /RST is driven high, the memory enters a normal operating mode after
the t
PU
time is satisfied. Driving /RST low during a read or write operation will abort the operation and data may
be lost.
Note: The FM25LX64 contains no power management circuits. To ensure proper operation, the user is
responsible for /RST being held active (low) while V
DD
voltage stabilizes and is within the specified DC
min/max limits. It is recommended that the part is not powered down with chip enable active.
SERIAL PERIPHERAL INTERFACE – SPI BUS
The FM25LX64 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 20
MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller.
Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate
the port using ordinary port pins for microcontrollers that do not. The FM25LX64 operates in SPI Mode 0 and 3.
The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system
configuration uses a single FM25LX64 device with a microcontroller that has a dedicated SPI port, as Figure 2
illustrates. Note that there may be additional delay required in the SO path to account for proper data output hold
timing. A one-gate buffer ‘1G125 is shown.
For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. Figure 3 shows a
configuration that uses the MCU GPIO pins.
Rev. 1.1
Feb. 2012
Page 3 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
SCK
MOSI
MISO
‘1G125
SO
SI
SCK
SPI
Microcontroller
FM25LX64
CS RST
SS
System
Reset
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select
Figure 2. System Configuration with SPI port
P1.0
P1.1
P1.2
Microcontroller
SO
SI SCK
FM25LX64
P1.3
CS
RST
System
Reset
Figure 3. System Configuration without SPI port
OPERATING VOLTAGE
It should be noted that the operating voltage range allow the use of 1.5V and 1.6V voltage regulators that are
spec’d to an output voltage of ±3%. A 1.5V regulator with a ±3% has a V
OUT
min of 1.455V and a max of
1.545V. A 1.6V regulator with a ±3% has a V
OUT
min of 1.552V and a max of 1.648V. The FM25LX64 is spec’d
to operate from V
DD
= 1.40V to 1.65V which meets both voltage rail tolerances.
Protocol Overview
The SPI interface is a synchronous serial interface using clock and data pins. Once chip select is activated by the
bus master, the FM25LX64 will begin monitoring the clock and data lines. The relationship between the falling
edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI
mode on the falling edge of each chip select. While there are four such modes, the FM25LX64 supports Modes 0
and 3. Figure 4 shows the required signal relationships for Modes 0 and 3. For both modes, data is clocked into
the FM25LX64 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If
the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising
edge.
The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /CS is
activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and
data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data
transfer.
Rev. 1.1
Feb. 2012
Page 4 of 14
FM25LX64 - 64Kb 1.5V SPI F-RAM
Important: The /CS pin must go inactive after an operation is complete and before a new op-code can be
issued. There is one valid op-code only per active chip select.
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Power Up to First Access
The FM25LX64 is not accessible for a period of time (t
PU
) after power up. Users must comply with the timing
parameter t
PU
, which is the minimum time from /RST deasserted to the first /CS low.
Data Transfer
All data transfers to and from the FM25LX64 occur in 8-bit groups. They are synchronized to the clock signal
(SCK), and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of SCK.
Outputs are driven from the rising edge of SCK. This is different compared to a standard SPI device.
Command Structure
There are six commands called op-codes that can be issued by the bus master to the FM25LX64. They are listed
in the table below. These op-codes control the functions performed by the memory. They can be divided into
three categories. First, there are commands that have no subsequent operations. They perform a single function
such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate
on the Status Register. The third group includes commands for memory transactions followed by address and one
or more bytes of data.
Table 1. Op-code Commands
Name
Description
Set Write Enable Latch
WREN
Write Disable
WRDI
Read Status Register
RDSR
Write Status Register
WRSR
Read Memory Data
READ
WRITE
Write Memory Data
Op-code
0000
0000
0000
0000
0000
0000
0110b
0100b
0101b
0001b
0011b
0010b
Hex
0x06
0x04
0x05
0x01
0x03
0x02
Rev. 1.1
Feb. 2012
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