LDS8160
Dual-Output
RGB
/ 6-Channel WLED Driver
with LED-Sense
TM
Temperature & Color Compensation
FEATURES
Six PowerLite
Linear LDO current drivers
with 25 mV drop-out in a common cathode
topology with up to 25 mA per channel
LED current programmable from 0 to 25 mA
in 200 linear steps
Three separately controlled driver banks (2
LED each) supports RGB LED applications.
Integrated digital temperature sensor with 10-
0
0
bit ADC; 1 C resolution with 5 C accuracy
TM
LED-Sense * temperature compensation
algorithm continually monitors LED V-I
parameters and adjusts brightness per user
loaded PWM correction
Three integrated PWM generators support
RGB color correction and dimming with 12-bit
resolution and 256 user programmable
logarithmic steps (~ 0.17 dB per step)
2
I C serial programming interface; additional
address pin allows 4 unique slave addresses.
Power efficiency up to 98%; average
efficiency > 80% in Li-ion battery applications
Low current shutdown mode (< 1 µA); Low
current software “standby mode” (< 5 µA)
Soft start and current limiting
LED Short circuit detection and protection, LED
open detection
Thermal shutdown protection
Low EMI.
Available in 3 x 3 x 0.8 mm
3
16-pin TQFN or ultra
small WCSP 3 x 4 ball grid (0.4mm pitch).
TM
Each channel contains a linear LDO current driver in
a common cathode (i.e., current source) topology.
The LDO drivers have a typical dropout voltage of
25mV at maximum rated current. This provides a low
power and low EMI solution in Li-ion battery
applications without voltage boosting and associated
external capacitors and components.
Three 12-bit PWM generators with “smooth”
logarithmic control support Temperature vs. LED
Luminosity adjustments as well, as RGB color
correction and dimming. The PWM generators are
2
programmable via an I C serial interface. User
programmed 8-bit codes are converted to 12-bit
resolution logarithmic steps of ~ 0.17 dB per step.
The PWM frequency is ~280 Hz to minimize noise.
The LED-Sense temperature compensation engine
includes a multiplexed 10-bit ADC and digital
processing circuits. The algorithm continually
measures the V-I characteristics of the LEDs and an
on-chip temperature diode to determine LED junction
temperatures to within 5ºC accuracy.
Three user-programmable temperature correction
tables (LUTs) store PWM adjustment codes for every
5ºC increment from -35ºC to 120ºC. These codes
drive the PWM engine to adjust for luminosity
variations and/or high temperature current de-rating.
The three correction LUTs support independent
correction for 3-color RGB applications.
The EN logic input functions as a chip enable. A logic
HIGH applied at EN allows the LDS8160 to respond
2
to I C communication. A serial address pin, SADD,
supports use in multi-target applications. The device
operates from 2.3V to 5.5V.
The LDS8160 is available in a 0.4mm pitch 12-ball
WCSP or a 3 x 3 x 0.8 mm 16-lead TQFN packages.
TM
APPLICATION
Keypad and Display Backlight
Cellular Phones
Digital Still Cameras
PDAs and Smartphones
DESCRIPTION
The LDS8160 is a dual-output RGB or 6-channel
white
LED
driver
with
three
temperature
compensation circuits for each bank of two LED
drivers. It supports both RGB LED and WLED
backlighting and keypad in portable applications.
Three 8-bit DACs set the current level for each LED
bank (A, B, & C) from 0 to 25mA in 0.125mA steps.
© 2009 IXYS Corp.
Characteristics subject to change without notice
1
Doc. No. 8160_DS, Rev. N1.0
LDS8160
ABSOLUTE MAXIMUM RATINGS
Parameter
V
IN
, LEDx
EN, SDAT, SCLK voltage
Storage Temperature Range
Junction Temperature Range
Soldering Temperature
HBM
ESD Protection Level
MM
Rating
6
V
IN
+ 0.7V
-65 to +160
-40 to +125
300
2
200
Unit
V
V
°C
°C
°C
kV
V
RECOMMENDED OPERATING CONDITIONS
Parameter
V
IN
I
LED
per LED pin
Total Output Current I
LOAD
Junction Temperature Range
EN pin Input Voltage @ LP Standby Mode
Rating
2.3 to 5.5
0 – 25
150
-40 to +125
1.8 ± 0.1
Unit
V
mA
mA
°C
V
Typical application circuit with external components is shown on page 1.
ELECTRICAL OPERATING CHARACTERISTICS
(Over recommended operating conditions unless specified otherwise) Vin = 3.6V, Cin = 1 µF, EN = High, T
AMB
= 25°C
Name
Conditions
Min
2
EN = 1.8 V
LP Standby (no I C clock)
2
EN = V
IN
Standby (no I C clock)
Quiescent Current
6 Channels at 100% DC
I
LOAD
= 120 mA
PWMs and Temp
I
LOAD
= 60 mA
Compensations Active
Shutdown Current
V
EN
= 0V
LED Current Accuracy
5mA
≤I
LED
≤25
mA
LED Channel Matching
(I
LED
- I
LEDAVG
) / I
LEDAVG
Line Regulation
2.7 V
≤V
IN
≤4.2
V
1
Load Regulation
0.2 V < Vdx < V
IN
-1.4 V
2
Dropout Voltage
5 mA
≤I
LED
≤25
mA
10
PWM Frequency
# of PWM duty cycle steps
Log & Linear Mode
Minimum PWM On Time
PWM resolution
PWM Step Size
PWM Adjustment Steps
of
Temperature Measurement Resolution
Temperature Measurement Accuracy
Input current
EN Pin
Logic Level
Input Current Limit
Thermal Shutdown
© 2009 IXYS Corp.
Characteristics subject to change without notice
Log Mode
Linear Mode
Log Mode
Linear Mode
1-x Scale Mode
(~ 0.17 dB per step)
2-x Scale Mode
(~ 0.34 dB per step)
Typ
5
125
0.6
0.4
0.5
±1.5
±1.5
2
0.8
25
285
256
13.7
12
8
0.17
I
LED
/256
Max
1
40
Units
µA
µA
mA
mA
µA
%
%
%/V
%/V
mV
Hz
µs
bits
bits
dB
-7
-7
1
5
+7
+7
PWM
0
Steps/5 C
0
0
C
C
High
Low
Active mode, EN = V
IN
LP Standby
Active Mode or Normal
Standby Mode
-1
5
1.2
1
µA
V
mA
°C
0.4
450
150
3
Doc. No. 8160_DS, Rev. N1.0
LDS8160
Name
Thermal Hysteresis
Wake-up Delay Time (EN Raising Edge)
Shutdown Delay Time (EN Falling Edge)
LED Driver PWM Ramp-Up time
2
(from PWM write command via I C)
3
Output short circuit Threshold
Note:
Conditions
Soft Ramp Disabled
Soft Ramping Enabled
(only wake-up)
I
LED
= 20 mA
Min
Typ
20
0.5
10
250
0.14
Max
Units
ms
ms
V
1. Vdx = Vin – V
F
,
2. Vdx = Vin – V
F
, at which I
ILED
decreases by 10% from set value
3. Minimum LED forward voltage, which will be interpreted as “LED SHORT” condition
I C CHARACTERISTICS
Over recommended operating conditions unless otherwise specified for 2.7
VIN
5.5V,
over full ambient temperature range -40 to +85ºC.
2
Symbol
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
BUF
t
AA
t
DH
Parameter
SCL Clock Frequency
Hold Time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up Time for a repeated START condition
Data In Hold Time
Data In Set-up Time
Rise Time of both SDAT and SCLK signals
Fall Time of both SDAT and SCLK signals
Set-up Time for STOP condition
Bus Free Time between a STOP and START condition
SCLK Low to SDAT Data Out and ACK Out
Data Out Hold Time
Min
0
0.6
1.3
0.6
0.6
0
100
Max
400
0.9
300
300
0.6
1.3
0.9
300
Unit
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
ns
Figure 1: I C Bus Timing Diagram
2
READ OPERATION:
Option 1:
Standard protocol sequential read:
S
Slave Address
R
A
Data 0
A
Data 1
A
Data 2
Reg. m+2
Data n
Reg. m+n,
A*
P
From: Reg. m
Reg. m+1
where Reg. m is the last addressed in the write operation register
Option 2:
Random access:
S
Slave Address
R
A
Data m
A*
P
From reg. m, where Reg. m is the last addressed in the write operation register
© 2009 IXYS Corp.
Characteristics subject to change without notice
4
Doc. No. 8160_DS, Rev. N1.0
LDS8160
Option 3:
Random access with combined (extended) protocol:
S
Slave Address
W
A
Register Address m
A
Sr
Slave Address
R
A
Data m
A*
P
WRITE OPERATION:
Option 1:
Standard protocol sequencial write:
S
Slave Address
W
A
Register Address m
A
Data 0
A
Data 1
Reg. m+1
A
Data 2
Reg. m+2
Data k
Reg. m+k
A*
P
To: Reg. m
At k = 4 data are send to register m and cycle repeats
Option 2:
Combined (extended) protocol:
S
Slave Address
W
A
Register Address m
A
Sr
Slave Address
W
A
Data
A*
P
To: Reg. m
S: Start Condition
Sr Start Repeat Condition
R, W: Read bit (1), Write bit (0)
A: Acknowledge (SDAT high)
A*: Not Acknowledge (SDAT low)
P: Stop Condition
Slave Address: Device address 7 bits (MSB first).
Register Address: Device register address 8 bits
Data: Data to read or write 8 bits
- send by master
- send by slave
I
2
C BUS PROTOCOL
Standard protocol
Combined protocol:
© 2009 IXYS Corp.
Characteristics subject to change without notice
5
Doc. No. 8160_DS, Rev. N1.0
FPGA/CPLD
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