The 87C196KD 16-bit microcontroller is a high-performance member of the MCS 96 microcontroller family
The 87C196KD is an enhanced 8XC196KC device with 1000 bytes RAM 16 MHz operation and 32 Kbytes of
on-chip EPROM Intel’s CHMOS process provides a high-performance processor along with low power con-
sumption
Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are
available for pulse or waveform generation The high-speed output can also generate four software timers or
start an A D conversion Events can be based on the timer or up down counter
NOTICE
This datasheet contains information on products in full production Specifications within this datasheet
are subject to change without notice Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design
MCS
96 is a registered trademark of Intel Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
January 1995
Order Number 272168-002
AUTOMOTIVE 87C196KD
272168 –1
Figure 1 87C196KD Block Diagram
272168– 2
Figure 2 The 87C196KD Family Nomenclature
87C196KD Enhanced Feature Set over the 87C196KC
1 The 87C196KD has twice the RAM and twice the EPROM of the 87C196KC
2 The vertical windowing scheme has been extended to allow all 1000 bytes of register RAM to be windowed
into the lower register file
3 A CLKOUT disable bit has been added to the IOC3 SFR This can be used to reduce noise in systems not
requiring the CLKOUT signal
2
AUTOMOTIVE 87C196KD
PACKAGING
PLCC
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
Description
ACH7 P0 7
ACH6 P0 6
ACH2 P0 2
ACH0 P0 0
ACH1 P0 1
ACH3 P0 3
NMI
EA
V
CC
V
SS
XTAL1
XTAL2
CLKOUT
BUSWIDTH
INST
ALE ADV
RD
AD0 P3 0
AD1 P3 1
AD2 P3 2
AD3 P3 3
AD4 P3 4
AD5 P3 5
PLCC
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
Description
AD6 P3 6
AD7 P3 7
AD8 P4 0
AD9 P4 1
AD10 P4 2
AD11 P4 3
AD12 P4 4
AD13 P4 5
AD14 P4 6
AD15 P4 7
T2CLK P2 3
READY
T2RST P2 4
BHE WRH
WR WRL
PWM0 P2 5
P2 7 T2CAPTURE
V
PP
V
SS
HSO 3
HSO 2
P2 6 T2UP-DN
P1 7 HOLD
PLCC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Description
P1 6 HLDA
P1 5 BREQ
HSO 1
HSO 0
HSO 5 HSI 3
HSO 4 HSI 2
HSI 1
HSI 0
P1 4 PWM2
P1 3 PWM1
P1 2
P1 1
P1 0
TXD P2 0
RXD P2 1
RESET
EXTINT P2 2
V
SS
V
REF
ANGND
ACH4 P 04
ACH5 P 05
Figure 3 68-Pin PLCC Functional Pin-out
3
AUTOMOTIVE 87C196KD
272168 –3
Figure 4 68-Pin PLCC Package
Table 1 Prefix Identification
PLCC
87C196KD
OTP Version
AN87C196KD
4
AUTOMOTIVE 87C196KD
PIN DESCRIPTIONS
Symbol
V
CC
V
SS
V
REF
Main supply voltage (5V)
Digital circuit ground (0V) There are three V
SS
pins all of which must be connected
Reference voltage for the A D converter (5V) V
REF
is also the supply voltage to the analog
portion of the A D converter and the logic used to read Port 0 Must be connected for A D
and Port 0 to function
Reference ground for the A D converter Must be held at nominally the same potential as
V
SS
Timing pin for the return from powerdown circuit Connect this pin with a 1
mF
capacitor to
V
SS
and a 1 MX resistor to V
CC
If this function is not used V
PP
may be tied to V
CC
This pin
is the programming voltage on the EPROM device
Input of the oscillator inverter and of the internal clock generator
Output of the oscillator inverter
Output of the internal clock generator The frequency of CLKOUT is
frequency
Reset input to the chip
Input for buswidth selection If CCR bit 1 is a one this pin selects the bus width for the bus
cycle in progress If BUSWIDTH is a 1 a 16-bit bus cycle occurs If BUSWIDTH is a 0 an
8-bit cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus
A positive transition causes a vector through 203EH
Output high during an external memory read indicates the read is an instruction fetch INST
is valid throughout the bus cycle INST is activated only during external memory accesses
and output low for a data fetch
Input for memory select (External Access) EA equal to a TTL-high causes memory
accesses to locations 2000H through 5FFFH to be directed to on-chip ROM EPROM EA
equal to a TTL-low causes accesses to those locations to be directed to off-chip memory
Address Latch Enable or Address Valid output as selected by CCR Both pin options
provide a signal to demultiplex the address from the address data bus When the pin is
ADV it goes inactive high at the end of the bus cycle ALE ADV is activated only during
external memory accesses
Read signal output to external memory RD is activated only during external memory reads
Write and Write Low output to external memory as selected by the CCR WR will go low for
every external write while WRL will go low only for external writes where an even byte is
being written WR WRL is activated only during external memory writes
Bus High Enable or Write High output to external memory as selected by the CCR BHE
e
0 selects the bank of memory that is connected to the high byte of the data bus A0
e
0
selects the bank of memory that is connected to the low byte of the data bus Thus
accesses to a 16-bit wide memory can be to the low byte only (A0
e
0 BHE
e
1) to the
high byte only (A0
e
1 BHE
e
0) or both bytes (A0
e
0 BHE
e
0) If the WRH function is
selected the pin will go low if the bus cycle is writing to an odd memory location BHE WRH
is valid only during 16-bit external memory write cycles
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