Data Sheet No. PD94139
IRU1261
DUAL 6A AND 1A LOW DROPOUT
POSITIVE FIXED 1.5V AND 2.5V REGULATOR
DESCRIPTION
The IRU1261, using a proprietary process, combines a
dual low dropout regulator with fixed outputs of 1.5V and
2.5V in a single package with the 1.5V output having a
minimum of 6A and the 2.5V having a 1A output current
capability. This product is specifically designed to pro-
vide well regulated supplies from 3.3V to generate 1.5V
for GTL+ termination resistor supply and 2.5V clock
supply for the new generation of the Pentium
II
TM
pro-
cessor applications.
FEATURES
Guaranteed to Provide 1.5V and 2.5V Supplies
with 3.1V Input
Fast Transient Response
1% Voltage Reference Initial Accuracy
Built-In Thermal Shutdown
APPLICATIONS
Pentium
II
TM
Processor Applications
TYPICAL APPLICATION
3.3V
C1
V
OUT
1
V
IN
5
4
3
2
1
C4
C2
C3
2.5V / 1A
IRU1261
Gnd
V
OUT
2
1.5V / 6A
V
CTRL
5V
R1
Figure 1 - Typical application of IRU1261 in a Pentium
II
TM
processor application.
Note:
Pentium
II
TM
is trademark of Intel Corp.
PACKAGE ORDER INFORMATION
T
J
(°C)
0 To 150
5-PIN PLASTIC
TO-263 (M)
IRU1261CM
5-PIN PLASTIC
Ultra Thin-Pak
TM
(P)
IRU1261CP
Rev. 2.0
09/19/02
www.irf.com
1
IRU1261
ABSOLUTE MAXIMUM RATINGS
Input Voltage (V
IN
) ....................................................
Power Dissipation .....................................................
Storage Temperature Range ......................................
Operating Junction Temperature Range .....................
7V
Internally Limited
-65°C To 150°C
0°C To 150°C
PACKAGE INFORMATION
5-PIN PLASTIC TO-263 (M)
5
4
3
2
1
5-PIN ULTRA THIN-PAK
TM
(P)
5
4
3
2
1
V
OUT
1
V
IN
Gnd
V
OUT
2
V
CTRL
V
OUT
1
V
IN
Gnd
V
OUT
2
V
CTRL
θ
JA
=308C/W for 1"sq pad
θ
JA
=308C/W for 1"sq pad
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over C =1mF, C
OUT
=100mF and T =0 to 1508C. Typical
IN
J
values refer to T
J
=258C. I
FL
=6A for output #2 and 1A for output #1. V
CTRL
=5V, V
IN
=3.3V.
PARAMETER
V
CTRL
Input Voltage
Output Voltage #2
Output Voltage #1
Line Regulation
Load Regulation (Note 1)
Dropout Voltage (Output #2)
Dropout Voltage (Output #1)
Current Limit (Output #2)
Current Limit (Output #1)
Minimum Load Current
Thermal Regulation
Ripple Rejection
Temperature Stability
Long Term Stability
RMS Output Noise
SYM
V
O2
V
O1
TEST CONDITION
Io=10mA, T
J
=25°C
Io=10mA
Io=10mA, T
J
=25°C
Io=10mA
Io=10mA, 3.1V<V
IN
<3.6V
10mA<Io<I
FL
Note 2, Io=6A, V
CTRL
=4.75V
Note 2, Io=1A, V
CTRL
=4.75V
DVo=100mV
DVo=100mV
Note 3
30ms Pulse, Io=I
FL
f=120Hz, Co=25mF Tantalum,
Io=0.5
3
I
FL
Io=10mA
T
J
=1258C, 1000Hrs
10Hz<f<10KHz
MIN
3.0
1.485
1.470
2.462
2.425
TYP
1.500
1.500
2.500
2.500
0.2
0.4
0.4
6.1
1.1
5
0.01
70
0.5
0.3
0.003
10
0.02
MAX
1.515
1.530
2.537
2.575
UNITS
V
V
V
%
%
V
V
A
A
mA
%/W
dB
%
%
%V
O
1.3
0.6
Note 1:
Low duty cycle pulse testing with Kelvin con-
nections is required in order to maintain accurate data.
Note 2:
Dropout voltage is defined as the minimum dif-
ferential voltage between V
IN
and V
OUT
required to main-
tain regulation at V
OUT
. It is measured when the output
voltage drops 1% below its nominal value.
Note 3:
Minimum load current is defined as the mini-
mum current required at the output in order for the out-
put voltage to maintain regulation. Typically the resistor
dividers are selected such that it automatically main-
tains this current.
2
www.irf.com
Rev. 2.0
09/19/02
IRU1261
PIN DESCRIPTIONS
PIN # PIN SYMBOL
1
V
CTRL
PIN DESCRIPTION
The control input pin of the regulator. This pin is connected, via a 10V resistor, to the 5V
supply to provide the base current for the pass transistor of both regulators. This allows
the regulator to have very low dropout voltage which allows one to generate a well regu-
lated 2.5V supply from the 3.3V input. A high frequency, 1mF capacitor is connected
between this pin and V
IN
pin to insure stability.
The output #2 (high current) of the regulator. A minimum of 100mF capacitor must be
connected from this pin to ground to insure stability.
This pin is connected to ground. It is also the Tab of the package.
The power input pin of the regulator. Typically a large storage capacitor is connected from
this pin to ground to insure that the input voltage does not sag below the minimum drop
out voltage during the load transient response. This pin must always be higher than both
V
OUT
pins by the amount of the dropout voltage (see data sheet) in order for the device to
regulate properly.
The output #1 (low current) of the regulator. A minimum of 100mF capacitor must be
connected from this pin to ground to insure stability.
2
V
OUT
2
3
4
Gnd
V
IN
5
V
OUT
1
BLOCK DIAGRAM
V
IN
4
V
CTRL
1
5 V
OUT
1
THERMAL
SHUTDOWN
1.20V
+
3 Gnd
2 V
OUT
2
Figure 2 - Simplified block diagram of the IRU1261.
Rev. 2.0
09/19/02
www.irf.com
3
IRU1261
APPLICATION INFORMATION
Introduction
The IRU1261 is a dual fixed output Low Dropout (LDO)
regulator available in a TO-263 package. This voltage
regulator is designed specifically for Pentium
II
proces-
sor applications requiring 2.5V and 1.5V supplies, elimi-
nating the need for a second regulator resulting in lower
overall system cost. The IRU1261 is designed to take
advantage of 5V supply to provide the drive for the pass
transistor, allowing 2.5V supply to be generated from
3.3V input. This feature improves the power dissipation
of the 2.5V regulator substantially allowing a smaller
heat sink to be used for the application. Compared to
the IRU1260 dual adjustable regulator, the IRU1261 in-
cludes the resistor dividers that are otherwise needed
with the IRU1260, eliminating four external components
and their tolerances, resulting in a more accurate initial
accuracy for each output voltage. Other features of the
device include: fast response to sudden load current
changes, such as GTL+ termination application and ther-
mal shutdown protection to protect the device if an over-
load condition occurs.
Stability
The IRU1261 requires the use of an output capacitor as
part of the frequency compensation in order to make the
regulator stable. Typical designs for the microprocessor
applications use standard electrolytic capacitors with
typical ESR in the range of 50 to 100mV and the output
capacitance of 500 to 1000mF. Fortunately as the ca-
pacitance increases, the ESR decreases resulting in a
fixed RC time constant. The IRU1261 takes advantage
of this phenomena in making the overall regulator loop
stable. For most applications a minimum of 100mF alu-
minum electrolytic capacitor with the maximum ESR of
0.3V such as Sanyo, MVGX series, Panasonic FA se-
ries as well as the Nichicon PL series insures both sta-
bility and good transient response. The IRU1261 also
requires a 1mF ceramic capacitor connected from V
IN
to
V
CTRL
and a 10V, 0.1W resistor in series with V
CTRL
pin
in order to further insure stability.
Thermal Design
The IRU1261 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Although this device can operate with junction tempera-
tures in the range of 1508C, it is recommended that the
selected heat sink be chosen such that during maxi-
mum continuous load operation the junction tempera-
ture is kept below this number. The example given shows
the steps in selecting the proper regulator heat sink for
driving the Pentium
II
processor GTL+ termination re-
sistors and the Clock IC using IRU1261 in TO-263 pack-
age.
Example
:
Assuming the following specifications:
V
IN
= 3.3V
V
OUT1
= 2.5V
V
OUT2
= 1.5V
I
OUT1(MAX)
= 0.2A
I
OUT2(MAX)
= 1.5A
T
A
= 358C
The steps for selecting a proper heat sink to keep the
junction temperature below 1358C is given as:
1) Calculate the maximum power dissipation using:
P
D
= I
OUT1
3(V
IN
- V
OUT1
) + I
OUT2
3(V
IN
- V
OUT2
)
P
D
= 0.23(3.3 - 2.5) + 1.53(3.3 - 1.5) = 2.86W
2) Assuming a TO-263 surface mount package, the junc-
tion to ambient thermal resistance of the package is:
u
JA
= 308C/W for 1" square pad area
3) The maximum junction temperature of the device is
calculated using the equation below:
T
J
= T
A
+ P
D
3u
JA
T
J
= 35 + 2.86330 = 1218C
Since this is lower than our selected 1358C maxi-
mum junction temperature (1508C is the thermal shut-
down of the device), TO-263 package is a suitable
package for our application.
Layout Consideration
The IRU1261 like all other high speed linear regulators
need to be properly laid out to insure stable operation.
The most important component is the output capacitor,
which needs to be placed close to the output pin and
connected to this pin using a plane connection with a
low inductance path.
4
www.irf.com
Rev. 2.0
09/19/02
FPGA/CPLD
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