®
X9251
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet
April 13, 2007
FN8166.5
Quad Digitally-Controlled (XDCP™)
Potentiometer
The X9251 integrates four digitally controlled potentio-
meters (XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are imple-mented
with a combination of resistor elements and CMOS switches.
The position of the wipers are controlled by the user through
the SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written to and
read by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls the
content of the default Data Registers of each DCP (DR00,
DR10, DR20, and DR30) to the corresponding WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Four potentiometers in one package
• 256 resistor taps–0.4% resolution
• SPI Serial Interface for write, read, and transfer operations
of the potentiometer
• Wiper resistance: 100Ω typical @ V
CC
= 5V
• 4 Non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper positions
• Standby current <5µA max
• V
CC
: 2.7V to 5.5V Operation
• 50kΩ, 100kΩ versions of total resistance
• 100 year data retention
• Single supply version of X9250
• Endurance: 100,000 data changes per bit per register
• 24 Ld SOIC, 24 Ld TSSOP
• Low power CMOS
• Pb-free plus anneal available (RoHS compliant)
Functional Diagram
V
CC
R
H0
R
H1
R
H2
R
H3
HOLD
A1
A0
SO
SI
SCK
CS
SPI
Interface
WCR0
DR00
DR01
DR02
DR03
DCP0
POWER UP,
INTERFACE
CONTROL
AND
STATUS
WCR1
DR10
DR11
DR12
DR13
DCP1
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
V
SS
WP
R
W0
R
L0
R
W1
R
L1
R
W2
R
L2
R
W3
R
L3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9251
Ordering Information
PART NUMBER
X9251US24
X9251US24Z (Note)
X9251UV24
X9251UV24Z (Note)
X9251TS24
X9251TS24Z (Note)
X9251TS24I
X9251TS24IZ (Note)
X9251TV24I
X9251TV24IZ (Note)
X9251US24I-2.7
PART
MARKING
X9251US
X9251US Z
X9251UV
X9251UV Z
X9251TS
X9251TS Z
X9251TS I
X9251TS ZI
X9251TV I
X9251TV ZI
X9251US G
2.7 to 5.5
50
100
V
CC
LIMITS
(V)
5 ±10%
POTENTIOMENTER
ORGANIZATION
TEMP RANGE
(kΩ)
(°C)
50
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
100
0 to +70
0 to +70
0 to +70
0 to +70
-40 to +85
-40 to +85
PACKAGE
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
PKG.
DWG. #
M24.3
M24.3
MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
M24.3
M24.3
M24.3
M24.3
MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
M24.3
M24.3
MDP0044
X9251US24IZ-2.7 (Note) X9251US ZG
X9251UV24-2.7
X9251UV24Z-2.7 (Note)
X9251UV24I-2.7
X9251UV F
X9251UV ZF
X9251UV G
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld TSSOP (4.4mm)
MDP0044
X9251UV24IZ-2.7 (Note) X9251UV ZG
X9251TS24-2.7
X9251TS24Z-2.7 (Note)
X9251TV24-2.7
X9251TV24Z-2.7 (Note)
X9251TV24I-2.7
X9251TV24IZ-2.7 (Note)
X9251TS F
X9251TS ZF
X9251TV F
X9251TV ZF
X9251TV G
X9251TV ZG
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
M24.3
M24.3
MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld TSSOP (4.4mm)
MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8166.5
April 13, 2007
X9251
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SO
A0
R
W3
R
H3
R
L3
NC
V
CC
R
L0
R
H0
R
W0
CS
WP
Pinout
X9251
(24 LD SOIC/TSSOP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
X9251
24
23
22
21
20
19
18
17
16
15
14
13
HOLD
SCK
R
L2
R
H2
R
W2
NC
V
SS
R
W1
R
H1
R
L1
A1
SI
Pin Assignments
PIN
(SOIC)
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
20
21
22
23
24
6, 19
NOTE:
1. A0 and A1 device address pins must be tied to a logic level.
SYMBOL
SO
A0
R
W3
R
H3
R
L3
V
CC
R
L0
R
H0
R
W0
CS
WP
SI
A1
R
L1
R
H1
R
W1
V
SS
R
W2
R
H2
R
L2
SCK
HOLD
NC
FUNCTION
Serial Data Output for SPI bus
Device Address for SPI bus. (See Note 1)
Wiper Terminal of DCP3
High Terminal of DCP3
Low Terminal of DCP3
System Supply Voltage
Low Terminal of DCP0
High Terminal of DCP0
Wiper Terminal of DCP0
SPI bus. Chip Select active low input
Hardware Write Protect - active low
Serial Data Input for SPI bus
Device Address for SPI bus. (See Note 1)
Low Terminal of DCP1
High Terminal of DCP1
Wiper Terminal of DCP1
System Ground
Wiper Terminal of DCP2
High Terminal of DCP2
Low Terminal of DCP2
Serial Clock for SPI bus
Device select. Pauses the SPI serial bus.
No Connect
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
3
FN8166.5
April 13, 2007
X9251
Pin Descriptions
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out by the falling edge
of the serial clock.
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte addresses
and data to be written to the device registers are input on
this pin. Data is latched by the rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9251.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while
SCK is LOW. To resume communication, HOLD is brought
HIGH, again while SCK is LOW. If the pause feature is not
used, HOLD should be held HIGH at all times.
DEVICE ADDRESS (A1 AND A0)
The address inputs are used to set the two least significant
bits of the slave address. A match in the slave address serial
data stream must be made with the address input in order to
initiate communication with the X9251. Device pins A1 and
A0 must be tied to a logic level which specifies the internal
address of the device, see Figures 2, 3, 4, 5 and 6.
CHIP SELECT (CS)
When CS is HIGH, the X9251 is deselected and the SO pin
is at high impedance, and (unless an internal write cycle is
underway) the device is in the standby state. CS LOW
enables the X9251, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
GROUND (V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is
the system ground.
Other Pins
NO CONNECT
No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents non-volatile writes to the
Data Registers.
Principles of Operation
The X9251 is an integrated circuit incorporating four DCPs
and their associated registers and counters, and a serial
interface providing direct communication between a host
and the potentiometers.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
pins). The RW pin is an
intermediate node, equivalent to the wiper terminal of a
mechanical potentiometer.
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer. Since there are
4 potentiometers, there are 4 sets of R
H
and R
L
such that
R
H0
and R
L0
are the terminals of DCP0 and so on.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of R
W
such that R
W0
is the terminals of
DCP0 and so on.
4
FN8166.5
April 13, 2007
X9251
One of Four Potentiometers
#: 0, 1, 2, or 3
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
8
DR#1
8
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR#)
SERIAL
BUS
INPUT
R
H
DR#2
DR#3
COUNTER
---
DECODE
DCP
CORE
R
W
IF WCR = 00[H] then R
W
is closet to R
L
IF WCR = FF[H] then R
W
is closet to R
H
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
UP/DN
CLK
R
L
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Power Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of V
CC
and the voltages applied to the
potentiometer pins provided that V
CC
is always more
positive than or equal to V
H
, V
L
, and V
W
(i.e., V
CC
≥
V
H
, V
L
,
V
W
). The V
CC
ramp rate specification is always in effect.
Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Counter Register. All
operations changing data in one of the Data Registers is a
non-volatile operation and takes a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Bits [7:0] are used to store one of the 256 wiper positions or
data (0 ~ 255).
Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers, one for
each potentiometer. The Wiper Counter Register can be
envisioned as a 8-bit parallel and serial load counter with its
outputs decoded to select one of 256 wiper positions along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
Wiper Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a
time by the Increment/Decrement instruction (See
Instruction section for more details). Finally, it is loaded with
the contents of its Data Register zero (DR#0) upon
power-up. (See Figure 1)
The wiper counter register is a volatile register; that is, its
contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the value
in DR#0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR#0 value
into the WCR#.
Status Register (SR)
This 1-bit Status Register is used to store the system status.
WIP: Write In Progress status bit, read only.
• When WIP = 1, indicates that high-voltage write cycle is in
progress.
• When WIP = 0, indicates that no high-voltage write cycle is
in progress.
5
FN8166.5
April 13, 2007
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
