®
X9259
Single Supply/Low Power/256-Tap/2-Wire bus
Data Sheet
April 13, 2007
FN8169.5
Quad Digitally-Controlled (XDCP™)
Potentiometers
The X9259 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2-wire bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written to and
read by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls the
content of the default Data Registers of each DCP (DR00,
DR10, DR20, and DR30) to the corresponding WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Four Separate Potentiometers in One Package
• 256 Resistor Taps–0.4% Resolution
• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer
• Wiper Resistance: 100Ω typical @ V
CC
= 5V
• 4 Non-volatile Data Registers for Each Potentiometer
• Non-volatile Storage of Multiple Wiper Positions
• Standby Current <5µA Max
• V
CC
: 2.7V to 5.5V Operation
• 50kΩ, 100kΩ versions of Total Resistance
• Endurance: 100,000 Data Changes per Bit per Register
• 100 year Data Retention
• Single Supply Version of X9258
• 24 Ld SOIC, 24 Ld TSSOP
• Low Power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
Functional Diagram
V
CC
R
H0
R
H1
R
H2
R
H3
A3
A2
A1
A0
SDA
SCL
2-Wire
Interface
POWER UP,
INTERFACE
CONTROL
AND
STATUS
WCR0
DR00
DR01
DR02
DR03
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
V
SS
WP
R
W0
R
L0
R
W1
R
L1
R
W2
R
L2
R
W3
R
L3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9259
Ordering Information
PART
NUMBER
X9259TS24
X9259TS24Z (Note)
X9259TS24I
X9259TS24IZ (Note)
X9259TV24I
X9259TV24IZ (Note)
X9259US24*
X9259US24Z* (Note)
X9259US24I
X9259US24IZ (Note)
X9259UV24I*
X9259UV24IZ* (Note)
X9259TS24-2.7*
X9259TS24Z-2.7* (Note)
X9259TS24I-2.7
X9259TS24IZ-2.7 (Note)
X9259TV24-2.7
X9259TV24Z-2.7 (Note)
X9259US24-2.7
X9259US24Z-2.7 (Note)
X9259US24I-2.7
X9259US24IZ-2.7 (Note)
X9259UV24-2.7*
X9259UV24Z-2.7 (Note)
X9259UV24I-2.7*
X9259UV24IZ-2.7* (Note)
PART MARKING
X9259TS
X9259TS Z
X9259TS I
X9259TS ZI
X9259TV I
X9259TV ZI
X9259US
X9259US Z
X9259US I
X9259US ZI
X9259UV I
X9259UV Z I
X9259TS F
X9259TS ZF
X9259TS G
X9259TS ZG
X9259TV F
X9259TV ZF
X9259US F
X9259US ZF
X9259US G
X9259US ZG
X9259UV F
X9259UV ZF
X9259UV G
X9259UV ZG
50
2.7 to 5.5
100
50
V
CC
LIMITS
(V)
5 ±10%
R
TOTAL
(kΩ)
100
TEMPERATURE
RANGE
(°C)
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
PACKAGE
24 Ld SOIC
24 Ld SOIC (Pb-free)
24 Ld SOIC
24 Ld SOIC (Pb-free)
24 Ld TSSOP
24 Ld TSSOP (Pb-free)
24 Ld SOIC
24 Ld SOIC (Pb-free)
24 Ld SOIC
24 Ld SOIC (Pb-free)
24 Ld TSSOP
24 Ld TSSOP (Pb-free)
24 Ld SOIC
24 Ld SOIC (Pb-free)
24 Ld SOIC
24 Ld SOIC (Pb-free)
24 Ld TSSOP
24 Ld TSSOP (Pb-free)
24 Ld SOIC
24 Ld SOIC (Pb-free)
24 Ld SOIC
24 Ld SOIC (Pb-free)
24 Ld TSSOP
24 Ld TSSOP (Pb-free)
24 Ld TSSOP
24 Ld TSSOP (Pb-free)
PKG. DWG. #
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
MDP0044
MDP0044
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "T1" suffix for tape and reel.
2
FN8169.5
April 13, 2007
X9259
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback
circuits
DNC
A0
R
W3
R
H3
R
L3
NC
V
CC
R
L0
R
H0
R
W0
A2
WP
Pin Configuration
SOIC/TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
X9259
24
23
22
21
20
19
18
17
16
15
14
13
A3
SCL
R
L2
R
H2
R
W2
NC
V
SS
R
W1
R
H1
R
L1
A1
SDA
Pin Assignments
PIN
(SOIC/
TSSOP)
2
3
4
5
6
7
8
9
10
11
12
13
SYMBOL
A0
R
W3
R
H3
R
L3
NC1
V
CC
R
L0
R
H0
R
W0
A2
WP
SDA
A1
R
L1
R
H1
R
W1
V
SS
R
W2
R
H2
R
L2
SCL
A3
NC
DNC
FUNCTION
Device Address for 2-Wire bus. (See Note 1)
Wiper Terminal of DCP3
High Terminal of DCP3
Low Terminal of DCP3
Must be left unconnected
System Supply Voltage
Low Terminal of DCP0
High Terminal of DCP0
Wiper Terminal of DCP0
Device Address for 2-Wire bus. (See Note 1)
Hardware Write Protect – Active Low
Serial Data Input/Output for 2-Wire bus.
Device Address for 2-Wire bus. (See Note 1)
Low Terminal of DCP1
High Terminal of DCP1
Wiper Terminal of DCP1
System Ground
Wiper Terminal of DCP2
High Terminal of DCP2
Low Terminal of DCP2
Serial Clock for 2-Wire bus.
Device Address for 2-Wire bus. (See Note 1)
No Connect
Do Not Connect
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
14
15
16
17
18
20
21
22
23
24
6, 19
1
Note 1:
A0 through A3 Device address pins must be tied to a logic
level.
3
FN8169.5
April 13, 2007
X9259
Pin Descriptions
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for a 2-
Wire slave device and is used to transfer data into and out of
the device. It receives device address, opcode, wiper
register address and data sent from a 2-Wire master at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock SCL.
It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open
drain output requires the use of a pull-up resistor.
SERIAL CLOCK (SCL)
This input is used by 2-Wire master to supply 2-Wire serial
clock to the X9259.
DEVICE ADDRESS (A3 THROUGH A0)
The Address inputs are used to set the least significant 4 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9259. A maximum
of 16 devices may occupy the 2-Wire serial bus. Device pins
A3 through A0 must be tied to a logic level which specifies
the external address of the device, see Figures 3, 4, and 5.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer. Since there are
4 potentiometers, there are 4 sets of R
H
and R
L
such that
R
H0
and R
L0
are the terminals of DCP0 and so on.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of R
W
such that R
W0
is the terminal of
DCP0 and so on.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
GROUND (V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is
the system ground.
Other Pins
NO CONNECT
No connect pins should be left open. This pins are used for
Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents non-volatile writes to the
Data Registers.
One of Four Potentiometers
#: 0, 1, 2, or 3
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
8
DR#1
8
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR#)
SERIAL
BUS
INPUT
R
H
DR#2
DR#3
COUNTER
---
DECODE
DCP
CORE
R
W
IF WCR = 00[H] then R
W
is closest to R
L
IF WCR = FF[H] then R
W
is closest to R
H
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
UP/DN
CLK
R
L
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
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FN8169.5
April 13, 2007
X9259
Principles of Operation
The X9259 is an integrated circuit incorporating four DCPs
and their associated registers and counters, and the serial
interface providing direct communication between a host
and the potentiometers.
written indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a
time by the Increment/Decrement instruction (see Instruction
section for more details). Finally, it is loaded with the
contents of its data register zero (DR#0) upon power-up.
(See Figure 1)
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9259 is powered-down.
Although the register is automatically loaded with the value
in DR#0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR#0 value
into the WCR# (See Design Considerations Section).
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
pins). The RW pin is an
intermediate node, equivalent to the wiper terminal of a
mechanical potentiometer.
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four data
registers and the associated Wiper Counter Register. All
operations changing data in one of the data registers is a
non-volatile operation and takes a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Bit [7:0] are used to store one of the 256 wiper positions
(0 ~ 255).
Power Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of V
CC
and the voltages applied to the
potentiometer pins provided that V
CC
is always more
positive than or equal to V
H
, V
L
, and V
W
, i.e., V
CC
≥
V
H
, V
L
,
V
W
. The V
CC
ramp rate specification is always in effect.
Wiper Counter Register (WCR)
The X9259 contains four Wiper Counter Registers, one for
each potentiometer. The Wiper Counter Register can be
envisioned as a 8-bit parallel and serial load counter with its
outputs decoded to select one of 256 wiper positions along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
Wiper Counter Register instruction (serial load); it may be
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]:
Used to store the current wiper position (Volatile).
WCR7
(MSB)
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
(LSB)
TABLE 2. DATA REGISTER, DR (8-BIT), BIT [7:0]:
Used to store wiper positions or data (Non-volatile).
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
5
FN8169.5
April 13, 2007
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