DATASHEET
X9269
Single Supply/Low Power/256-Tap/2-Wire Bus Dual Digitally-Controlled (XDCP™)
Potentiometers
FEATURES
• Dual–Two Separate Potentiometers
• 256 Resistor Taps/Pot–0.4% Resolution
• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer Single
Supply Device
•
Wiper Resistance, 100 Typical V
CC
= 5V
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on
Power-up.
• Standby Current < 5µA Max
• 50k, 100k Versions of End to End Pot
Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 24-Lead SOIC, 24-Lead TSSOP
• Low Power CMOS
• Power Supply V
CC
= 2.7V to 5.5V
• Pb-Free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9269 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-Wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default Data Register (DR0)
to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FN8173
Rev.4.00
April 17, 2007
FUNCTIONAL DIAGRAM
V
CC
R
H0
R
H1
2-Wire
Bus
Interface
Address
Data
Status
Bus
Interface
and Control
Write
Read
Transfer
Inc/Dec
Power-on Recall
Wiper Counter
Registers (WCR)
Control
Data Registers
(DR0–DR3)
V
SS
R
W0
R
L0
R
W1
R
L1
50k or 100k versions
FN8173 Rev.4.00
April 17, 2007
Page 1 of 24
X9269
Ordering Information
PART NUMBER
X9269TS24*
X9269TS24I*
X9269TS24IZ* (Note)
X9269TS24Z* (Note)
X9269TV24
X9269US24*
X9269US24I*
X9269US24IZ* (Note)
X9269US24Z* (Note)
X9269UV24*
X9269UV24I
X9269TS24-2.7*
X9269TS24I-2.7*
X9269TS24IZ-2.7* (Note)
X9269TS24Z-2.7* (Note)
X9269TV24I-2.7
X9269TV24IZ-2.7* (Note)
X9269US24-2.7*
X9269US24I-2.7*
X9269US24IZ-2.7* (Note)
X9269US24Z-2.7* (Note)
X9269UV24-2.7*
X9269UV24I-2.7*
X9269UV24IZ-2.7*
PART
MARKING
X9269TS
X9269TS I
X9269TS ZI
X9269TS Z
X9269TV
X9269US
X9269US I
X9269US ZI
X9269US Z
X9269UV
X9269UV I
X9269TS F
X9269TS G
X9269TS ZG
X9269TS ZF
X9269TV G
X9269TV ZG
X9269US F
X9269US G
X9269US ZG
X9269US ZF
X9269UV F
X9269UV G
X9269UV ZG
50
2.7 to 5.5
100
50
V
CC
LIMITS
(V)
5 ±10%
POTENTIOMETER
ORGANIZATION
(k)
100
TEMP
RANGE
(°C)
0 to +70
PACKAGE
24 Ld SOIC (300 mil)
PKG.
DWG. #
M24.3
M24.3
M24.3
M24.3
MDP0044
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
MDP0044
-40 to +85 24 Ld SOIC (300 mil)
-40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
0 to +70
0 to +70
0 to +70
24 Ld SOIC (300 mil)
(Pb-free)
24 Ld TSSOP (4.4mm)
24 Ld SOIC (300 mil)
-40 to +85 24 Ld SOIC (300 mil)
-40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
0 to +70
0 to +70
24 Ld SOIC (300 mil)
(Pb-free)
24 Ld TSSOP (4.4mm)
-40 to +85 24 Ld TSSOP (4.4mm)
0 to +70
24 Ld SOIC (300 mil)
-40 to +85 24 Ld SOIC (300 mil)
-40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
0 to +70
24 Ld SOIC (300 mil)
(Pb-free)
-40 to +85 24 Ld TSSOP (4.4mm)
-40 to +85 24 Ld TSSOP (4.4mm)
(Pb-free)
0 to +70
24 Ld SOIC (300 mil)
-40 to +85 24 Ld SOIC (300 mil)
-40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
0 to +70
0 to +70
24 Ld SOIC (300 mil)
(Pb-free)
24 Ld TSSOP (4.4mm)
-40 to +85 24 Ld TSSOP (4.4mm)
-40 to +85 24 Ld TSSOP (4.4mm)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8173 Rev.4.00
April 17, 2007
Page 2 of 24
X9269
DETAILED FUNCTIONAL DIAGRAM
R
H0
R
L0
R
W0
V
CC
Power-on
Recall
R
0
R
1
Wiper
Counter
Register
(WCR)
Pot 0
SCL
SDA
A3
A2
A1
A0
WP
INTERFACE
AND
CONTROL
CIRCUITRY
R
2
R
3
50k and 100k
256-taps
8
Data
Power-on
Recall
R
0
R
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
R
2
R
3
V
SS
R
L1
R
H1
R
W1
CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for com-
parators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage
amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF cir-
cuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment sys-
tems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
FN8173 Rev.4.00
April 17, 2007
Page 3 of 24
X9269
PIN CONFIGURATION
SOIC/TSSOP
NC
A0
NC
NC
NC
NC
V
CC
R
L0
R
H0
R
W0
A2
WP
1
2
3
4
5
6
7
8
9
10
11
12
X9269
24
23
22
21
20
19
18
17
16
15
14
13
A3
SCL
NC
NC
NC
NC
V
SS
R
W1
R
H1
R
L1
A1
SDA
PIN ASSIGNMENTS
Pin
(SOIC/TSSOP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
NC
A0
NC
NC
NC
NC
V
CC
R
L0
R
H0
R
W0
A2
WP
SDA
A1
R
L1
R
H1
R
W1
V
SS
NC
NC
NC
NC
SCL
A3
No Connect
Device Address for 2-Wire bus.
No Connect
No Connect
No Connect
No Connect
System Supply Voltage
Low Terminal for Potentiometer 0.
High Terminal for Potentiometer 0.
Wiper Terminal for Potentiometer 0.
Device Address for 2-Wire bus.
Hardware Write Protect
Function
Serial Data Input/Output for 2-Wire bus.
Device Address for 2-Wire bus.
Low Terminal for Potentiometer 1.
High Terminal for Potentiometer 1.
Wiper Terminal for Potentiometer 1.
System Ground
No Connect
No Connect
No Connect
No Connect
Serial Clock for 2-Wire bus.
Device Address for 2-Wire bus.
FN8173 Rev.4.00
April 17, 2007
Page 4 of 24
X9269
PIN DESCRIPTIONS
Bus Interface Pins
S
ERIAL
D
ATA
I
NPUT
/O
UTPUT
(SDA)
The SDA is a bidirectional serial data input/output pin for
a 2-Wire slave device and is used to transfer data into
and out of the device. It receives device address,
opcode, wiper register address and data sent from an 2-
Wire master at the rising edge of the serial clock SCL,
and it shifts out data after each falling edge of the serial
clock SCL.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor.
For selecting typical values, refer to the guidelines for
calculating typical values on the bus pull-up resistors
graph.
S
ERIAL
C
LOCK
(SCL)
This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9269.
D
EVICE
A
DDRESS
(A3 - A0)
The address inputs are used to set the least significant 4
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with the
X9269. A maximum of 16 devices may occupy the 2-
Wire serial bus.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer. Since there
are 2 potentiometers, there are 2 sets of R
H
and R
L
such that R
H0
and R
L0
are the terminals of POT 0 and
so on.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4
potentiometers, there are 2 sets of R
W
such that R
W0
is
the terminal of POT 0 and so on.
Bias Supply Pins
S
YSTEM
S
UPPLY
V
OLTAGE
(V
CC
)
AND
S
UPPLY
G
ROUND
(V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin
is the system ground.
Other Pins
N
O
C
ONNECT
No connect pins should be left open. This pins are used
for Intersil manufacturing and testing purposes.
H
ARDWARE
W
RITE
P
ROTECT
I
NPUT
(WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
FN8173 Rev.4.00
April 17, 2007
Page 5 of 24
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
