®
X9401
Low Noise/Low Power/SPI Bus
Data Sheet
October 12, 2006
FN8190.3
Quad, 64 Tap, Digitally Controlled
Potentiometer (XDCP™)
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
Quad–4 separate pots, 64 taps/pot
Nonvolatile storage of wiper position
Four Nonvolatile Data Registers for Each Pot
16-bytes of EEPROM memory
SPI serial interface
R
Total
= 10kΩ
Wiper resistance = 150Ω typical
Standby current < 1µA (total package)
Operating current < 400µA max.
V
CC
= 2.7V to 5V
Package–24 Ld SOIC
100 year data retention
Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9401 integrates 4 digitally controlled potentiome-
ters (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented
using 64 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4 nonvola-
tile Data Registers (DR0:DR3) that can be directly writ-
ten to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of
DR0 to the WCR.
The XDCP can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.
BLOCK DIAGRAM
V
CC
V
SS
R0 R1
Pot 0
Wiper
Counter
Register
(WCR)
V
H0
/R
H0
R0 R1
Wiper
Counter
Register
(WCR)
V
H2
/R
H2
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
Data
R2 R3
V
L0
/R
L0
V
W0
/R
W0
R2 R3
Resistor
Array
Pot 2
V
L2
/R
L2
V
W2
/R
W2
8
V
W1
/R
W1
R0 R1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
V
H1
/R
H1
R0 R1
Wiper
Counter
Register
(WCR)
V
W3
/R
W3
V
H3
/R
H3
R2 R3
V
L1
/R
L1
R2 R3
Resistor
Array
Pot 3
V
L3
/R
L3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9401
Ordering Information
PART NUMBER
X9401WS24IZ (Note)
X9401WS24I-2.7*
X9401WS24IZ-2.7* (Note)
PART
MARKING
X9401WS ZI
X9401WS G
X9401WS ZG
V
CC
LIMITS
(V)
5 ±10%
2.7 to 5.5
POTENTIOMETER
TEMP
ORGANIZATION (kΩ) RANGE (°C)
10
10
-40 to 85
-40 to 85
-40 to 85
PACKAGE
24 Ld SOIC (300 mil) (Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
PKG. DWG.
#
MDP0027
M24.3
MDP0027
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9401.
Chip Select (CS)
When CS is HIGH, the X9401 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9401, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence
is underway, HOLD may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause, HOLD must be brought LOW
while SCK is LOW. To resume communication, HOLD is
brought HIGH, again while SCK is LOW. If the pause
feature is not used, HOLD should be held HIGH at all
times.
Device Address (A
0
-
A
1
)
The address inputs are used to set the least significant 2
bits of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address
input in order to initiate communication with the
X9401. A maximum of 4 devices may occupy the SPI
serial bus.
Potentiometer Pins
V
H
(V
H0
- V
H3
), V
L
(V
L0
- V
L3
), R
H
(R
H0
- R
H3
),
R
L
(R
L0
- R
L3
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the
terminal connections on either end of a mechanical poten-
tiometer.
V
W
(V
W0
- V
W3
), R
W
(R
W0
- R
W3
)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Wiper Counter Registers.
2
FN8190.3
October 12, 2006
X9401
PIN CONFIGURATION
SOIC
V
CC
V
L0
/R
L0
V
H0
/R
H0
V
W0
/R
W0
CS
WP
SI
A
1
V
L1
/R
L1
V
H1
/R
H1
V
W1
/R
W1
V
SS
Array Description
NC
V
L3
/R
L3
V
H3
/R
H3
V
W3
/R
W3
A
0
SO
HOLD
SCK
V
L2
/R
L2
V
H2
/R
H2
V
W2
/R
W2
NC
1
2
3
4
5
6
7
8
9
10
11
12
X9401
24
23
22
21
20
19
18
17
16
15
14
13
The X9401 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
Wiper Counter Register (WCR)
The X9401 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is equiv-
alent to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by
the host via the Write Wiper Counter Register instruc-
tion (serial load); it may be written indirectly by trans-
ferring the contents of one of four associated data
registers via the XFR Data Register or Global XFR
Data Register instructions (parallel load); it can be
modified one step at a time by the Increment/Decre-
ment instruction. Finally, it is loaded with the contents
of its data register zero (R0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9401 is powered-
down. Although the register is automatically loaded
with the value in R
0
upon power-up, this may be differ-
ent from the value present at power-down. The wiper
position must be stored in R
0
to insure restoring the
wiper position after power-up.
Data Registers
Each potentiometer has four 6-bit nonvolatile data reg-
isters. These can be read or written directly by the
host. Data can also be transferred between any of the
four data registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the data registers can
be used as memory locations for system parameters
or user preference data.
PIN NAMES
Symbol
SCK
SI, SO
A
0
- A
1
V
H0
/R
H0
- V
H3
/R
H3
,
V
L0
/R
L0
- V
L3
/R
L3
V
W0
/R
W0
- V
W1
/R
W1
WP
V
CC
V
SS
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometers (terminal
equivalent)
Potentiometers (wiper
equivalent)
Hardware Write Protection
System Supply Voltage
System Ground
No Connection
DEVICE DESCRIPTION
The X9401 is a highly integrated microcircuit incorpo-
rating four resistor arrays and their associated regis-
ters and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9401 supports the SPI interface hardware con-
ventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
3
FN8190.3
October 12, 2006
X9401
Data Register Detail
(MSB)
D5
NV
D4
NV
D3
NV
D2
NV
D1
NV
(LSB)
D0
NV
I3
I2
I1
I0
Figure 2. Instruction Byte Format
Register
Select
R1
R0
P1
P0
Write in Process
The contents of the Data Registers are saved to non-
volatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a Write In Process bit (WIP).
The WIP bit is read with a Read Status command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9401 from the host, follow-
ing a CS going HIGH to LOW, is called the Identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9401 this
is fixed as 0101[B] (refer to Figure 1).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A
0
- A
1
input
pins. The X9401 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9401 to successfully
continue the command sequence. The A
0
- A
1
inputs
can be actively driven by CMOS input signals or tied to
V
CC
or V
SS
.
The remaining two bits in the slave byte must be set to 0.
Figure 1. Identification Byte Format
Device Type
Identifier
Instructions
Pot Select
The four high order bits of the instruction byte specify
the operation. The next two bits (R
1
and R
0
) select
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P
0
) selects which one of the four potenti-
ometers is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Global XFR Data Register to Wiper Counter Register
—This transfers the contents of all specified Data
Registers to the associated Wiper Counter Regis-
ters.
– Global XFR Wiper Counter Register to Data
Register—This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
The basic sequence of the two byte instructions is illus-
trated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by t
WRL
. A transfer from
the WCR (current wiper position), to a data register is a
write to nonvolatile memory and takes a minimum of
t
WR
to complete. The transfer can occur between one
of the four potentiometers and one of its associated reg-
isters; or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9401; either between the host and
0
1
0
1
0
0
A1
A0
Device Address
Instruction Byte
The next byte sent to the X9401 contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable,
they point to one of four associated registers. The for-
mat is shown below in Figure 2.
4
FN8190.3
October 12, 2006
X9401
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:
– Read Wiper Counter Register— read the current
wiper position of the selected pot,
– Write Wiper Counter Register—change current
wiper position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The sequence of these operations is shown in Figure 4
and Figure 5.
The final command is Increment/Decrement. It is dif-
ferent from the other commands, because it’s length is
indeterminate. Once the command is issued, the mas-
ter can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tun-
ing capability to the host. For each SCK clock pulse
(t
HIGH
) while SI is HIGH, the selected wiper will move
one resistor segment towards the V
H
/R
H
terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the V
L
/R
L
terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figure 6 and Figure 7.
Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
From Interface
Circuitry
Register 0
8
Register 1
6
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Serial
Bus
Input
C
o
u
n
t
e
r
D
e
c
o
d
e
V
H
/R
H
Register 2
Register 3
If WCR = 00[H] then V
W
/R
W
= V
L
/R
L
If WCR = 3F[H] then V
W
/R
W
= V
H
/R
H
UP/DN
Modified SCL
INC/DEC
Logic
UP/DN
CLK
V
L
/R
L
V
W
/R
W
5
FN8190.3
October 12, 2006
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