®
X9410
Low Noise/Low Power/SPI Bus
Data Sheet
October 12, 2006
FN8193.2
Dual Digitally Controlled Potentiometer
(XDCP™)
FEATURES
• Two potentiometers per package
• SPI serial interface
• Register oriented format
- Direct read/write/transfer wiper positions
- Store as many as four positions per
potentiometer
• Power supplies
- V
CC
= 2.7V to 5.5V
- V+ = 2.7V to 5.5V
- V- = -2.7V to -5.5V
• Low power CMOS
- Standby current < 1µA
- High reliability
- Endurance - 100,000 data changes per bit per
register
- Register data retention - 100 years
• 8-bytes of nonvolatile EEPROM memory
• 10kΩ resistor arrays
• Resolution: 64 taps each pot
• 24 Ld SOIC, 24 Ld TSSOP, and 24 Ld plastic DIP
packages
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
V
CC
V
SS
V+
V-
HOLD
CS
SCK
SO
SI
A0
A1
WP
DESCRIPTION
The X9410 integrates two digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
Pot 0
R0 R1
Wiper
Counter
Register
(WCR)
V
H0
/R
H0
R2 R3
V
L0
/R
L0
V
W0
/R
W0
Interface
and
Control
Circuitry
Data
8
Pot 1
R0 R1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot1
V
W1
/R
W1
V
H1
/R
H1
R2 R3
V
L1
/R
L1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9410
Ordering Information
PART NUMBER
X9410YS24I
X9410YS24IZ (Note)
X9410WP24I
X9410WS24I*
X9410WS24IZ* (Note)
X9410WV24I*
X9410WV24IZ* (Note)
X9410YS24I-2.7
X9410YS24IZ-2.7 (Note)
X9410WP24I-2.7
X9410WS24I-2.7*
POTENTIOMETER
V
CC
LIMITS ORGANIZATION TEMP RANGE
(kΩ)
(°C)
(V)
PART MARKING
X9410YS I
X9410YS ZI
X9410WP I
X9410WS I
X9410WS ZI
X9410WV I
X9410WV ZI
X9410YS G
X9410YS ZG
X9410WP G
X9410WS G
10
2.7 to 5.5
2.5
10
5 ±10%
2.5
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld PDIP
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
PKG. DWG. #
M24.3
MDP0027
E24.6
M24.3
MDP0027
MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld PDIP
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
M24.3
MDP0027
E24.6
M24.3
MDP0027
MDP0044
X9410WS24IZ-2.7* (Note) X9410WS ZG
X9410WV24-2.7*
X9410WV F
X9410WV24Z-2.7* (Note) X9410WV ZF
X9410WV24I-2.7*
X9410WV G
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld TSSOP (4.4mm)
MDP0044
X9410WV24IZ-2.7* (Note) X9410WV ZG
*Add "T1" suffix for tape and reel.
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9410.
Chip Select (CS)
When CS is HIGH, the X9410 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9410, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A
0
-
A
1
)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9410. A maximum of 4 devices may occupy the
SPI serial bus.
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October 12, 2006
X9410
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
- V
H1
/R
H1
), V
L
/R
L
(V
L0
/R
L0
- V
L1
/R
L1
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V
W
/R
W
(V
W0
/R
W0
- V
W1
/R
W1
)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
DIP/SOIC
V
CC
V
L0
/R
L0
V
H0
/R
H0
V
W0
/R
W0
CS
WP
SI
A
1
V
L1
/R
L1
V
H1
/R
H1
V
W1
/R
W1
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
X9410
24
23
22
21
20
19
18
17
16
15
14
13
V+
NC
NC
NC
A
0
SO
HOLD
SCK
NC
NC
NC
V-
PIN NAMES
Symbol
SCK
S
I
, S
O
A
0
- A
1
V
H0
/R
H0
- V
H1
/R
H1
,
V
L0
/R
L0
- V
L1
/R
L1
V
W0
/R
W0
- V
W1
/R
W1
WP
V+,V-
V
CC
V
SS
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometer Pins
(terminal equivalent)
Potentiometer Pin
(wiper equivalent)
Hardware Write Protection
Analog Supplies
System Supply Voltage
System Ground
No Connection
DEVICE DESCRIPTION
The X9410 is a highly integrated microcircuit
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9410 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
TSSOP
SI
A
1
V
L1
/R
L1
V
H1
/R
H1
V
W1
/R
W1
V
SS
NC
NC
NC
V-
SCK
HOLD
1
2
3
4
5
6
7
8
9
10
11
12
X9410
24
23
22
21
20
19
18
17
16
15
14
13
WP
CS
V
W0
/R
W0
V
H0
/R
H0
V
L0
/R
L0
V
CC
NC
NC
NC
V+
A
0
SO
The X9410 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
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FN8193.2
October 12, 2006
X9410
Wiper Counter Register (WCR)
The X9410 contains two Wiper Counter Registers, one
for each XDCP potentiometer. The WCR is equivalent
to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by the
host via the Write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated Data Registers
via the XFR Data Register or Global XFR Data Register
instructions (parallel load); it can be modified one step
at a time by the Increment/ Decrement instruction.
Finally, it is loaded with the contents of its Data Register
zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9410 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Figure 1. Detailed Potentiometer Block Diagram
(One of Two Arrays)
Serial Data Path
From Interface
Circuitry
Register 0
8
Register 1
6
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Data Registers
Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Data Register Detail
(MSB)
D5
NV
D4
NV
D3
NV
D2
NV
D1
NV
(LSB)
D0
NV
Serial
Bus
Input
C
o
u
n
t
e
r
D
e
c
o
d
e
V
H
/R
H
Register 2
Register 3
If WCR = 00[H] then V
W
/R
W
= V
L
/R
L
If WCR = 3F[H] then V
W
/R
W
= V
H
/R
H
UP/DN
Modified SCL
INC/DEC
Logic
UP/DN
CLK
V
L
/R
L
V
W
/R
W
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FN8193.2
October 12, 2006
X9410
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a Write In Process bit
(WIP). The WIP bit is read with a Read Status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9410 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9410 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A
0
- A
1
input
pins. The X9410 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9410 to successfully
continue the command sequence. The A
0
- A
1
inputs
can be actively driven by CMOS input signals or tied to
V
CC
or V
SS
.
The remaining two bits in the ID byte must be set to 0.
Figure 2. Identification Byte Format
Device Type
Identifier
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
0
P0
Instructions
Pot Select
The four high order bits of the instruction byte specify
the operation. The next two bits (R
1
and R
0
) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last bit (P
0
)
selects which one of the two potentiometers is to be
affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Global XFR Data Register to Counter Register—This
transfers the contents of both specified Data Registers
to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data
Register—This transfers the contents of both Wiper
Counter Registers to the specified associated Data
Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
WRL
. A transfer
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of t
WR
to complete. The transfer can occur
between one of the two potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between both potentiometers and
one associated register.
0
1
0
1
0
0
A1
A0
Device Address
Instruction Byte
The next byte sent to the X9410 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 3.
5
FN8193.2
October 12, 2006
FPGA/CPLD
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