NOT RECOMMENDED FOR NEW DESIGNS
INTERSIL SUGGESTS THE
ISL22316 OR ISL22319
DATASHEET
FN8197
Rev 1.00
April 26, 2006
X9428 Low Noise/Low Power/2-Wire Bus
Single Digitally Controlled Potentiometer (XDCP™)
FEATURES
• Solid state potentiometer
• 2-wire serial interface
• Register oriented format
—Direct Read/Write/Transfer wiper position
—Store as many as four positions per
potentiometer
• Power supplies
—V
CC
= 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low power CMOS
—Standby current < 1µA
—Ideal for battery operated applications
• High reliability
—Endurance–100,000 Data changes per bit per
register
—Register data retention–100 years
• 4-bytes of nonvolatile memory
• 10k resistor array
• Resolution: 64 taps each potentiometer
• 16 Ld SOIC, 14 Ld TSSOP packages
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9428 integrates a digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
V
CC
V
SS
V+
V–
SCL
SDA
A0
A2
A3
WP
R0 R1
Interface
and
Control
Circuitry
Data
V
H
/R
H
8
R2 R3
Wiper
Counter
Register
(WCR)
V
L
/R
L
V
W
/R
W
FN8197 Rev 1.00
April 26, 2006
Page 1 of 21
X9428 Low Noise/Low Power/2-Wire Bus
Ordering Information
PART NUMBER
X9428WS16*
X9428WS16Z* (Note)
X9428WS16I*
PART
MARKING
X9428WS
X9428WS Z
X9428WS I
V
CC
LIMITS (V)
5 to ±10%
POTENTIOMETER
ORGANIZATION (k)
10
TEMP. RANGE
(°C)
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
2
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
2.7 to 5.5
10
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
2
0 to +70
0 to +70
PACKAGE
PKG. DWG. #
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3
(Pb-free)
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3
(Pb-free)
14 Ld TSSOP
(4.4mm)
14 Ld TSSOP
(4.4mm) (Pb-free)
14 Ld TSSOP
(4.4mm)
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
M14.173
M14.173
M14.173
X9428WS16IZ* (Note) X9428WS ZI
X9428WV14*
X9428WV14Z* (Note)
X9428WV14I*
X9428 W
X9428 Z
X9428 WI
X9428WV14IZ* (Note) X9428 ZI
X9428YS16*
X9428YS16Z* (Note)
X9428YS16I*
X9428YS16IZ* (Note)
X9428YV14*
X9428YV14Z* (Note)
X9428YV14I*
X9428YV14IZ* (Note)
X9428WS16-2.7*
X9428WS16Z-2.7*
(Note)
X9428WS16I-2.7*
X9428WS16IZ-2.7*
(Note)
X9428WV14-2.7*
X9428WV14Z-2.7*
(Note)
X9428WV14I-2.7*
X9428WV14IZ-2.7*
(Note)
X9428YS16-2.7*
X9428YS16Z-2.7*
(Note)
X9428YS
X9428YS Z
X9428YS I
X9428YS ZI
X9428 Y
X9428 YZ
X9428 YI
X9428 YZI
X9428WS F
X9428WS ZF
X9428WS G
X9428WS ZG
X9428 WF
X9428 ZF
X9428 WG
X9428 ZG
X9428YS F
X9428YS ZF
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3
(Pb-free)
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3
(Pb-free)
14 Ld TSSOP
(4.4mm)
14 Ld TSSOP
(4.4mm) (Pb-free)
14 Ld TSSOP
(4.4mm)
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
M14.173
M14.173
M14.173
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3
(Pb-free)
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3
(Pb-free)
14 Ld TSSOP
(4.4mm)
14 Ld TSSOP
(4.4mm) (Pb-free)
14 Ld TSSOP
(4.4mm)
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
M14.173
M14.173
M14.173
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3
(Pb-free)
FN8197 Rev 1.00
April 26, 2006
Page 2 of 21
X9428 Low Noise/Low Power/2-Wire Bus
Ordering Information
(Continued)
PART NUMBER
X9428YS16I-2.7*
X9428YS16IZ-2.7*
(Note)
X9428YV14-2.7*
X9428YV14Z-2.7*
(Note)
X9428YV14I-2.7*
X9428YV14IZ-2.7*
(Note)
PART
MARKING
X9428YS G
X9428YS ZG
X9428 YF
X9428 YZF
X9428 YG
X9428 YZG
V
CC
LIMITS (V)
2.7 to 5.5
POTENTIOMETER
ORGANIZATION (k)
2
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
PACKAGE
PKG. DWG. #
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3
(Pb-free)
14 Ld TSSOP
(4.4mm)
14 Ld TSSOP
(4.4mm) (Pb-free)
14 Ld TSSOP
(4.4mm)
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
M14.173
M14.173
M14.173
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8197 Rev 1.00
April 26, 2006
Page 3 of 21
X9428 Low Noise/Low Power/2-Wire Bus
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9428.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs. An open drain output requires the use
of a pull-up resistor. For selecting typical values, refer to
the guidelines for calculating typical values on the bus
pull-up resistors graph.
Device Address (A
0
,
A
2
,
A
3
)
The Address inputs are used to set the least significant 3
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with the
X9428. A maximum of 8 devices may occupy the 2-wire
serial bus.
Potentiometer Pins
R
H
/V
H
, R
L
/V
L
The R
H
/V
H
and R
L
/V
L
inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
R
W
/V
W
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input WP
The WP pin when low prevents nonvolatile writes to the
Data Registers.
Analog Supply V+, V-
The Analog Supply V+, V- are the supply voltages for
the XDCP analog section.
PIN NAMES
Symbol
SCL
SDA
A0, A2, A3
R
H
/V
H
, V
L
/R
H
R
W
/V
W
WP
V+,V-
V
CC
V
SS
NC
Serial clock
Serial data
Device address
Potentiometer Pins
(terminal equivalent)
Potentiometer Pin (wiper equivalent)
Hardware write protection
Analog and voltage follower
System supply voltage
System ground
No connection
V
CC
A2
R
L
/V
L
R
H
/V
H
R
W
/V
W
SDA
WP
V
SS
1
2
3
4
5
6
7
8
X9428
PIN CONFIGURATION
DIP/SOIC
16
15
14
13
12
11
10
9
V+
NC
A0
NC
A3
SCL
NC
V-
TSSOP
A2
R
L
R
H
R
W
SDA
WP
V
SS
1
2
3
4
5
6
7
X9428
14
13
12
11
10
9
8
V
CC
V+
A0
NC
A3
SCL
V-
Description
FN8197 Rev 1.00
April 26, 2006
Page 4 of 21
X9428 Low Noise/Low Power/2-Wire Bus
PRINCIPLES OF OPERATION
The X9428 is a highly integrated microcircuit
incorporating a resistor array and its associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9428 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9428 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (tLOW). SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9428 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
HIGH
). The X9428 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condition
is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data.
0
The X9428 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command
byte. If the command is followed by a data byte the
X9428 will respond with a final acknowledge.
Array Description
The X9428 is comprised of a resistor array. The array
contains 63 discrete resistive segments that are
connected in series. The physical ends of the array are
equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the
WCR can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9428 this is
fixed as 0101[B].
Figure 1. Slave Address
Device Type
Identifier
1
0
1
A3
A2
0
A0
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A
0
, A
2
, A
3
inputs. The X9428 compares the
serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9428 to respond with an acknowledge. The A
0
,
A
2
, A
3
inputs can be actively driven by CMOS input
signals or tied to V
CC
or V
SS
.
FN8197 Rev 1.00
April 26, 2006
Page 5 of 21
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