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NDE ITUTE P , X9520
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329
REC LE SUB 6, ISL22
Data Sheet
N O T SSI B
2232
PO
, ISL
20
X958
X9521
Dual DCP, EEPROM Memory
January 3, 2006
FN8207.1
Fiber Channel/Gigabit Ethernet Laser
Diode Control for Fiber Optic Modules
FEATURES
• Two Digitally Controlled Potentiometers (DCP’s)
—100 Tap - 10kΩ
—256 Tap - 100kΩ
—Non-Volatile
—Write Protect Function
• 2kbit EEPROM Memory with Write Protect & Block
Lock
TM
• 2-Wire industry standard Serial Interface
—Complies to the Gigabit Interface Converter
(GBIC) specification
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• 20 Ld TSSOP
BLOCK DIAGRAM
DESCRIPTION
The X9521 combines two Digitally Controlled Potentiom-
eters (DCP’s), and integrated EEPROM with Block
Lock
TM
protection. All functions of the X9521 are
accessed by an industry standard 2-Wire serial interface.
The DCP’s of the X9521 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The 2kbit integrated EEPROM may be
used to store module definition data.
The features of the X9521 are ideally suited to simplifying
the design of fiber optic modules which comply to the Gi-
gabit Interface Converter (GBIC) specification. The inte-
gration of these functions into one package significantly
reduces board area, cost and increases reliability of laser
diode modules.
R
H1
WIPER
COUNTER
REGISTER
R
W1
R
L1
8
WP
PROTECT LOGIC
7 - BIT
NONVOLATILE
MEMORY
CONSTAT
R
H2
WIPER
COUNTER
REGISTER
SDA
SCL
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
4
REGISTER
R
W2
R
L2
2kbit
8 - BIT
NONVOLATILE
MEMORY
EEPROM
ARRAY
THRESHOLD
RESET LOGIC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9521
Ordering Information
PART NUMBER
X9521V20I-A
X9521V20I-B
X9521V20IZ-A (Note)
X9521V20IZ-B (Note)
PART MARKING
X9521VIA
X9521VIB
X9521VZIA
X9521VZIB
PRESET (FACTORY SHIPPED) V
TRIPx
THRESHOLD LEVELS (x = 2, 3)
Optimized for 3.3V system monitoring
Optimized for 5V system monitoring
Optimized for 3.3V system monitoring
Optimized for 5V system monitoring
TEMP RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
20 Ld TSSOP
20 Ld TSSOP
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN CONFIGURATION
20 Pin TSSOP
R
H2
R
W2
R
L2
NC
NC
NC
WP
SCL
SDA
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vcc
NC
NC
NC
NC
NC
NC
R
H1
R
W1
R
L1
PIN ASSIGNMENT
Pin
1
2
3
Name
R
H2
R
w2
R
L2
Function
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP2.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is
enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Pro-
tection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then
no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position
of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-
down” resistor, thus if left floating the write protection feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input
and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the de-
vice. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.
Ground.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1
Connection to end of resistor array for (the 100 Tap) DCP 1.
Supply Voltage.
No connect.
7
WP
8
9
10
11
12
13
20
4, 5, 6,
14, 15,
16, 17,
18, 19
SCL
SDA
Vss
R
L1
R
w1
R
H1
Vcc
NC
2
FN8207.1
January 3, 2006
X9521
SCL
SDA
Start
Figure 2.
Stop
Valid Start and Stop Conditions
SCL
SDA
Data Stable
Figure 1.
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Data Change
Data Stable
Valid Data Changes on the SDA Bus
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. The STOP condition is also used to
place the device into the Standby power mode after a
read sequence. A STOP condition can only be issued
after the transmitting device has released the bus. See
Figure 2.
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive opera-
tions. Therefore, the X9521 operates as a slave in all
applications.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The transmit-
ting device, either master or slave, will release the bus
after transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to ACKNOWL-
EDGE that it received the eight bits of data. Refer to
Figure 3.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If
a write operation is selected, the device will respond with
an ACKNOWLEDGE after the receipt of each subse-
quent eight bit word.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data. The device will ter-
minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.
FN8207.1
January 3, 2006
Serial Clock and Data
Data states on the SDA line can change only while SCL
is LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions.
See Figure 1. On power-up of the X9521, the SDA pin is
in the input mode.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.
3
X9521
SCL
from
Master
Data Output
from
Transmitter
Data Output
from
Receiver
1
8
9
Start
Figure 3.
Acknowledge
Acknowledge Response From Receiver
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 000 internally
selects the EEPROM array, while setting these bits to
111 selects the DCP structures in the X9521. The
CONSTAT Register may be selected using the Inter-
nal Device Address 010.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9521
can be split up into three main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—EEPROM array
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on each
of these individual parts, a 1, 2 or 3 Byte protocol is used.
All operations however must begin with the Slave
Address Byte being issued on the SDA pin. The Slave
address selects the part of the X9521 to be addressed,
and specifies if a Read or Write operation is to be per-
formed.
It should be noted that in order to perform a write opera-
tion to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 12.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9521.
SA7
SA6 SA5
SA4
SA3
SA2
SA1
SA0
1 0 1
DEVICE TYPE
IDENTIFIER
0
INTERNAL
DEVICE
ADDRESS
R/W
READ /
WRITE
Internal Address
(SA3 - SA1)
Internally Addressed
Device
EEPROM Array
CONSTAT Register
DCP
000
010
111
Bit SA0
0
1
Operation
WRITE
READ
Figure 4.
Slave Address Format
4
FN8207.1
January 3, 2006
X9521
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CONSTAT Register) has been correctly
issued (including the final STOP condition), the X9521
initiates an internal high voltage write cycle. This cycle
typically requires 5 ms. During this time, no further Read
or Write commands can be issued to the device. Write
Acknowledge Polling is used to determine when this high
voltage write cycle has been completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is still
busy with the high voltage cycle then no ACKNOWL-
EDGE will be returned. If the device has completed the
write operation, an ACKNOWLEDGE will be returned
and the host can then proceed with a read or write opera-
tion. (Refer to Figure 5.).
N
R
Hx
WIPER
COUNTER
REGISTER
(WCR)
DECODER
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
NON
VOLATILE
MEMORY
(NVM)
2
1
0
R
Lx
R
Wx
Figure 6.
DCP Internal Structure
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
The X9521 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
Hx
and R
Lx
inputs - where x = 1,2).
Issue STOP
Issue Slave Address
Byte (Read or Write)
ACK
returned?
YES
High Voltage Cycle
complete. Continue
command sequence?
YES
Continue normal
Read or Write
command sequence
NO
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(R
w
x
) output. Within each individual array, only one
switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.
On power-up of the X9521, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.
DCP
R
1
/ 100 TAP
R
2
/ 256 TAP
Initial Values Before Recall
V
L
/ TAP = 0
V
H
/ TAP = 255
NO
Issue STOP
PROCEED
Figure 5.
Acknowledge Polling Sequence
5
FN8207.1
January 3, 2006
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