®
X9C102, X9C103, X9C104, X9C503
Data Sheet
December 20, 2006
FN8222.1
Digitally Controlled Potentiometer
(XDCP™)
FEATURES
• Solid-state potentiometer
• 3-wire serial interface
• 100 wiper tap points
—Wiper position stored in nonvolatile memory
and recalled on power-up
• 99 resistive elements
—Temperature compensated
—End to end resistance, ±20%
—Terminal voltages, ±5V
• Low power CMOS
—V
CC
= 5V
—Active current, 3mA max.
—Standby current, 750µA max.
• High reliability
—Endurance, 100,000 data changes per bit
—Register data retention, 100 years
• X9C102 = 1kΩ
• X9C103 = 10kΩ
• X9C503 = 50kΩ
• X9C104 = 100kΩ
• Packages
—8 Ld SOIC and 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
U/D
INC
CS
V
CC
(Supply Voltage)
7-Bit
Up/Down
Counter
DESCRIPTION
The X9Cxxx are Intersil digitally controlled (XDCP)
potentiometers. The device consists of a resistor
array, wiper switches, a control section, and nonvola-
tile memory. The wiper position is controlled by a
three-wire interface.
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switch-
ing network. Between each element and at either end
are tap points accessible to the wiper terminal. The
position of the wiper element is controlled by the CS,
U/D, and INC inputs. The position of the wiper can be
stored in nonvolatile memory and then be recalled
upon a subsequent power-up operation.
The device can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including:
– control
– parameter adjustments
– signal processing
99
98
97
R
H
/V
H
Up/Down
(U/D)
Increment
(INC)
Device
Select (CS)
V
H
/R
H
Control
and
Memory
R
W
/V
W
V
L
/R
L
V
SS
(Ground)
General
7-Bit
Nonvolatile
Memory
96
One
of
One-
Hundred
Decoder
2
1
0
Transfer
Gates
Resistor
Array
V
CC
GND
Store and
Recall
Control
Circuitry
R
L
/V
L
R
W
/V
W
Detailed
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9C102, X9C103, X9C104, X9C503
PIN CONFIGURATION
DIP/SOIC
INC
U/D
V
H
/R
H
V
SS
1
2
3
4
X9C102/103/104/503
8
7
6
5
V
CC
CS
V
L
/R
L
V
W
/R
W
ORDERING INFORMATION
PART NUMBER
X9C102P
X9C102PZ (Note)
X9C102PI
X9C102PIZ (Note)
X9C102S*
,
**
X9C102SZ* (Note)
X9C102SI*
,
**
X9C102SIZ*
,
**
X9C103P
X9C103PZ (Note)
X9C103PI
X9C103PIZ (Note)
X9C103S*
,
**
X9C103SZ*
,
** (Note)
X9C103SI*
,
**
X9C103SIZ*
,
** (Note)
X9C503P
X9C503PZ (Note)
X9C503PI
X9C503PIZ (Note)
X9C503S*
X9C503SZ* (Note)
X9C503SI*
,
**
X9C503SIZ*
,
** (Note)
X9C104P
X9C104PI
X9C104PIZ (Note)
X9C104S*
,
**
X9C104SZ*
,
** (Note)
X9C104SI*
,
**
X9C104SIZ*
,
** (Note)
(Note)
PART MARKING
X9C102P
X9C102P Z
X9C102P I
X9C102P ZI
X9C102S
X9C102S Z
X9C102S I
X9C102S ZI
X9C103P
X9C103P Z
X9C103P I
X9C103P ZI
X9C103S
X9C103S Z
X9C103S I
X9C103S ZI
X9C503P
X9C503P Z
X9C503P I
X9C503P ZI
X9C503S
X9C503S Z
X9C503S I
X9C503S ZI
X9C104P
X9C104P I
X9C104P ZI
X9C104S
X9C104S Z
X9C104S I
X9C104S ZI
100
50
10
R
TOTAL
(kΩ)
1
TEMPERATURE RANGE
(°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld PDIP
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
PKG. DWG. #
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "T1" suffix for tape and reel.
**Add "T2" suffix for tape and reel.
2
FN8222.1
December 20, 2006
X9C102, X9C103, X9C104, X9C503
PIN DESCRIPTIONS
Pin
1
2
3
Symbol
INC
U/D
R
H
/V
H
Brief Description
Increment .
The INC input is negative-edge triggered. Toggling INC will move the wiper and either
increment or decrement the counter in the direction indicated by the logic level on the U/D input.
Up/Down.
The U/D input controls the direction of the wiper movement and whether the counter
is incremented or decremented.
R
H
/V
H
.
The high (V
H
/R
H
) terminals of the X9C102/103/104/503 are equivalent to the fixed
terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V.
The terminology of V
H
/R
H
and V
L
/R
L
references the relative position of the terminal in
relation to wiper movement direction selected by the U/D input and not the voltage potential on
the terminal.
4
5
V
SS
V
SS
V
W
/R
W
R
L
/V
L
V
W
/R
W
.
V
W
/R
W
is the wiper terminal, and is equivalent to the movable terminal of a mechanical
potentiometer. The position of the wiper within the array is determined by the control inputs. The
wiper terminal series resistance is typically 40Ω.
R
L
/V
L
.
The low (V
L
/R
L
) terminals of the X9C102/103/104/503 are equivalent to the fixed
terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V.
The terminology of V
H
/R
H
and V
L
/R
L
references the relative position of the terminal in
relation to wiper movement direction selected by the U/D input and not the voltage potential on
the terminal.
CS.
The device is selected when the CS input is LOW. The current counter value is stored in
nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store op-
eration is complete the X9C102/103/104/503 device will be placed in the low power standby mode
until the device is selected once again.
V
CC
6
7
CS
8
V
CC
3
FN8222.1
December 20, 2006
X9C102, X9C103, X9C104, X9C503
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on CS, INC, U/D and V
CC
with respect to V
SS
.................................. -1V to +7V
Voltage on V
H
/R
H
and V
L
/R
L
referenced to V
SS
................................... -8V to +8V
ΔV
= |V
H
/R
H
- V
L
/R
L
|
X9C102 ............................................................... 4V
X9C103, X9C503, and X9C104 ......................... 10V
Lead temperature (soldering, 10 seconds) ...... +300°C
I
W
(10 seconds) ................................................. 8.8mA
Power rating X9C102 ........................................ 16mW
Power rating X9C103/104/503 .......................... 10mW
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Supply Voltage (V
CC
)
X9C102/103/104/503
Limits
5V ±10%
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
R
TOTAL
V
VH/RH
V
VL/RL
I
W
R
W
Parameter
End to end resistance variation
V
H
terminal voltage
V
L
terminal voltage
Wiper current
Wiper resistance
Noise
(5)
Resolution
Absolute linearity
(1)
Relative linearity
(2)
RTOTAL temperature coefficient
RTOTAL temperature coefficient
Ratiometric temperature coefficient
Min.
-20
-5
-5
-4.4
Typ.
Max.
+20
+5
+5
4.4
Unit
%
V
V
mA
Ω
dBV
%
Test Conditions/Notes
40
-120
1
-1
-0.2
±300
(5)
±600
(5)
±20
10/10/25
100
Wiper Current = ±1mA
Ref. 1kHz
V
W(n)(actual)
- V
W(n)(expected)
V
W(n + 1)(actual)
- [V
W(n) + MI
]
X9C103/503/104
X9C102
See Circuit #3, Macro Model
+1
+0.2
MI
(3)
MI
(3)
ppm/°C
ppm/°C
ppm/°C
pF
C
H
/C
L
/C
W
(5)
Potentiometer capacitances
Notes: (1)
(2)
(3)
(4)
(5)
Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V
W(n)(actual)
- V
W(n)(expected )
] = ±1 MI Maximum.
Relative linearity is a measure of the error in step size between taps = V
W(n + 1)
- [V
W(n) + MI
] = +0.2 MI.
1 MI = Minimum Increment = R
TOT
/99
Typical values are for T
A
= +25°C and nominal supply voltage.
This parameter is not 100% tested.
4
FN8222.1
December 20, 2006
X9C102, X9C103, X9C104, X9C503
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
I
CC
I
SB
I
LI
V
IH
V
IL
C
IN(5)
Parameter
V
CC
active current
Standby supply current
CS, INC, U/D input leakage
current
CS, INC, U/D input HIGH
voltage
CS, INC, U/D input LOW
voltage
CS, INC, U/D input
capacitance
Min. Typ.
(4)
1
200
Max.
3
750
±10
Unit
mA
µA
µA
V
Test Conditions
CS = V
IL
, U/D = V
IL
or V
IH
and
INC = 0.4V to 2.4V @ max. t
CYC
CS = V
CC
- 0.3V, U/D and INC = V
SS
or V
CC
- 0.3V
V
IN
= V
SS
to V
CC
2
0.8
10
V
pF
V
CC
= 5V, V
IN
= V
SS
, T
A
= 25°C, f = 1MHz
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
years
Test Circuit #1
V
R
/R
H
V
S
Test Circuit #2
V
H
/R
H
Test Point
Test Point
V
W
/R
W
V
L
/R
L
V
W
/R
W
Force
Current
V
L
/R
L
Test Circuit #3
Macro Model
R
L
C
L
10pF
R
TOTAL
C
H
C
W
25pF
R
W
10pF
R
H
A.C. CONDITIONS OF TEST
Input pulse levels
Input rise and fall times
Input reference levels
0V to 3V
10ns
1.5V
5
FN8222.1
December 20, 2006
FPGA/CPLD
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