NXP Semiconductors
Mask Set Errata
KINETIS_K_2N96T
Rev. 04 AUG 2017
Mask Set Errata for Mask 2N96T
This report applies to mask 2N96T for these products:
• MK28FN2M0CAU15R
• MK28FN2M0VMI15
• MK27FN2M0VMI15
Table 1. Errata and Information Summary
Erratum ID
e8992
e6939
e9004
e9005
e6940
e9380
e9265
e10856
e9308
e10990
e10779
e10527
e10656
e9878
e7735
e10806
e10780
e11033
e9462
Erratum Title
AWIC: Early NMI wakeup not detected upon entry to stop mode from VLPR mode
Core: Interrupted loads to SP can cause erroneous behavior
Core: ITM can deadlock when global timestamping is enabled
Core: Store immediate overlapping exception return operation might vector to incorrect interrupt
Core: VDIV or VSQRT instructions might not complete correctly when very short ISRs are used
FlexIO: Reading FlexIO register when FlexIO functional clock is disabled results in a bus hang
FTM: Incorrect match may be generated if intermediate load feature is used in toggle mode
FTM: Safe state is not removed from channel outputs after fault condition ends if SWOCTRL is being
used to control the pin
I2C: I2C does not hold bus between byte transfers in receive and may result in lost data
I2S/SAI: I2S1 logic tied to I2S0 clock gate
Kinetis ROM Bootloader: Programming QuadSPI using bootloader over UART peripheral will fail due
to incorrect baud rate detection
LPUART: Setting and immediately clearing SBK bit can result in transmission of two break characters
LPUART: The RXD Pin Active Edge Interrupt flag does not assert when an active edge is detected
MCG: Clock transition may have an issue immediately after writing the OSCSEL or RANGE bit fields in
MCG control registers
MCG: IREFST status bit may set before the IREFS multiplexor switches the FLL reference clock
OCRAM: Does not support successive accesses to the same address
OCRAM: Un-aligned INCR burst transfers are not supported for eSDHC/USBHS/USBFS modules
OCRAM: With certain write/read sequences accessed from 0x3400_0000 to 0x3407_FFFF, data
corruption will occur
QuadSPI: DQS Learning/Calibration does not supports concurrent read transactions
Table continues on the next page...
Table 1. Errata and Information Summary (continued)
Erratum ID
e9651
e9461
e3981
e3982
e4624
e3977
e4627
e3984
e3983
e3978
e8807
e9646
Erratum Title
QuadSPI: QuadSPI SDR clock limitation when core clock is greater than 100MHz
QuadSPI: Read data errors may occur with data learning in 4x sampling method
SDHC: ADMA fails when data length in the last descriptor is less or equal to 4 bytes
SDHC: ADMA transfer error when the block size is not a multiple of four
SDHC: AutoCMD12 and R1b polling problem
SDHC: Does not support Infinite Block Transfer Mode
SDHC: Erroneous CMD CRC error and CMD Index error may occur on sending new CMD during data
transfer
SDHC: eSDHC misses SDIO interrupt when CINT is disabled
SDHC: Problem when ADMA2 last descriptor is LINK or NOP
SDHC: Software can not clear DMA interrupt status bit after read operation
USB: In Host mode, transmission errors may occur when communicating with a Low Speed (LS)
device through a USB hub
WDOG:Unexpected watchdog behavior on LLS exit
Table 2. Revision History
Revision
21 FEB 2017
04 AUG 2017
Initial revision
The following errata were added.
•
•
•
•
•
e10527
e11033
e10856
e10990
e10656
Changes
e8992: AWIC: Early NMI wakeup not detected upon entry to stop mode from VLPR
mode
Description:
Upon entry into VLPS from VLPR, if NMI is asserted before the VLPS entry completes, then
the NMI does not generate a wakeup to the MCU. However, the NMI interrupt will occur after
the MCU wakes up by another wake-up event.
Workaround:
There are two workarounds:
1) First transition from VLPR mode to RUN mode, and then enter into VLPS mode from RUN
mode.
2) Assert NMI signal for longer than 16 bus clock cycles.
Mask Set Errata for Mask 2N96T, Rev. 04 AUG 2017
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NXP Semiconductors
e6939: Core: Interrupted loads to SP can cause erroneous behavior
Description:
ARM Errata 752770: Interrupted loads to SP can cause erroneous behavior
This issue is more prevalent for user code written to manipulate the stack. Most compilers will
not be affected by this, but please confirm this with your compiler vendor. MQX™ and
FreeRTOS™ are not affected by this issue.
Affects: Cortex-M4, Cortex-M4F
Fault Type: Programmer Category B
Fault Status: Present in: r0p0, r0p1 Open.
If an interrupt occurs during the data-phase of a single word load to the stack-pointer (SP/
R13), erroneous behavior can occur. In all cases, returning from the interrupt will result in the
load instruction being executed an additional time. For all instructions performing an update to
the base register, the base register will be erroneously updated on each execution, resulting in
the stack-pointer being loaded from an incorrect memory location.
The affected instructions that can result in the load transaction being repeated are:
1) LDR SP,[Rn],#imm
2) LDR SP,[Rn,#imm]!
3) LDR SP,[Rn,#imm]
4) LDR SP,[Rn]
5) LDR SP,[Rn,Rm]
The affected instructions that can result in the stack-pointer being loaded from an incorrect
memory address are:
1) LDR SP,[Rn],#imm
2) LDR SP,[Rn,#imm]!
Conditions:
1) An LDR is executed, with SP/R13 as the destination.
2) The address for the LDR is successfully issued to the memory system.
3) An interrupt is taken before the data has been returned and written to the stack-pointer.
Implications:
Unless the load is being performed to Device or Strongly-Ordered memory, there should be no
implications from the repetition of the load. In the unlikely event that the load is being
performed to Device or Strongly-Ordered memory, the repeated read can result in the final
stack-pointer value being different than had only a single load been performed.
Interruption of the two write-back forms of the instruction can result in both the base register
value and final stack-pointer value being incorrect. This can result in apparent stack corruption
and subsequent unintended modification of memory.
Workaround:
Most compilers are not affected by this, so a workaround is not required.
However, for hand-written assembly code to manipulate the stack, both issues may be worked
around by replacing the direct load to the stack-pointer, with an intermediate load to a general-
purpose register followed by a move to the stack-pointer.
Mask Set Errata for Mask 2N96T, Rev. 04 AUG 2017
NXP Semiconductors
3
If repeated reads are acceptable, then the base-update issue may be worked around by
performing the stack pointer load without the base increment followed by a subsequent ADD or
SUB instruction to perform the appropriate update to the base register.
e9004: Core: ITM can deadlock when global timestamping is enabled
Description:
ARM ERRATA 806422
The Cortex-M4 processor contains an optional Instrumentation Trace Macrocell (ITM). This
can be used to generate trace data under software control, and is also used with the Data
Watchpoint and Trace (DWT) module which generates event driven trace. The processor
supports global timestamping. This allows count values from a system-wide counter to be
included in the trace stream.
When connected directly to a CoreSight funnel (or other component which holds ATREADY
low in the idle state), the ITM will stop presenting trace data to the ATB bus after generating a
timestamp packet. In this condition, the ITM_TCR.BUSY register will indicate BUSY.
Once this condition occurs, a reset of the Cortex-M4 is necessary before new trace data can
be generated by the ITM.
Timestamp packets which require a 5 byte GTS1 packet, or a GTS2 packet do not trigger this
erratum. This generally only applies to the first timestamp which is generated.
Devices which use the Cortex-M optimized TPIU (CoreSight ID register values 0x923 and
0x9A1) are not affected by this erratum.
Workaround:
There is no software workaround for this erratum. If the device being used is susceptible to this
erratum, you must not enable global timestamping.
e9005: Core: Store immediate overlapping exception return operation might vector to
incorrect interrupt
Description:
ARM Errata 838869: Store immediate overlapping exception return operation might vector to
incorrect interrupt
Affects: Cortex-M4, Cortex-M4F
Fault Type: Programmer Category B Rare
Fault Status: Present in: r0p0, r0p1 Open.
The Cortex-M4 includes a write buffer that permits execution to continue while a store is
waiting on the bus. Under specific timing conditions, during an exception return while this
buffer is still in use by a store instruction, a late change in selection of the next interrupt to be
taken might result in there being a mismatch between the interrupt acknowledged by the
interrupt controller and the vector fetched by the processor.
Configurations Affected
This erratum only affects systems where writeable memory locations can exhibit more than
one wait state.
Workaround:
For software not using the memory protection unit, this erratum can be worked around by
setting DISDEFWBUF in the Auxiliary Control Register.
Mask Set Errata for Mask 2N96T, Rev. 04 AUG 2017
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NXP Semiconductors
In all other cases, the erratum can be avoided by ensuring a DSB occurs between the store
and the BX instruction. For exception handlers written in C, this can be achieved by inserting
the appropriate set of intrinsics or inline assembly just before the end of the interrupt function,
for example:
ARMCC:
...
__schedule_barrier();
__asm{DSB};
__schedule_barrier();
}
GCC:
...
__asm volatile (“dsb 0xf” ::: “memory”);
}
e6940: Core: VDIV or VSQRT instructions might not complete correctly when very
short ISRs are used
Description:
ARM Errata 709718: VDIV or VSQRT instructions might not complete correctly when very
short ISRs are used
Affects: Cortex-M4F
Fault Type: Programmer Category B
Fault Status: Present in: r0p0, r0p1 Open.
On Cortex-M4 with FPU, the VDIV and VSQRT instructions take 14 cycles to execute. When
an interrupt is taken a VDIV or VSQRT instruction is not terminated, and completes its
execution while the interrupt stacking occurs. If lazy context save of floating point state is
enabled then the automatic stacking of the floating point context does not occur until a floating
point instruction is executed inside the interrupt service routine.
Lazy context save is enabled by default. When it is enabled, the minimum time for the first
instruction in the interrupt service routine to start executing is 12 cycles. In certain timing
conditions, and if there is only one or two instructions inside the interrupt service routine, then
the VDIV or VSQRT instruction might not write its result to the register bank or to the FPSCR.
Workaround:
A workaround is only required if the floating point unit is present and enabled. A workaround is
not required if the memory system inserts one or more wait states to every stack transaction.
There are two workarounds:
1) Disable lazy context save of floating point state by clearing LSPEN to 0 (bit 30 of the
FPCCR at address 0xE000EF34).
2) Ensure that every interrupt service routine contains more than 2 instructions in addition to
the exception return instruction.
Mask Set Errata for Mask 2N96T, Rev. 04 AUG 2017
NXP Semiconductors
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