FeaTures
n
n
LTC4300-1/LTC4300-2
Hot Swappable
2-Wire Bus Buffers
DescripTion
The
LTC
®
4300
series hot swappable 2-wire bus buffers
allow I/O card insertion into a live backplane without cor-
ruption of the data and clock busses. When the connection
is made, the LTC4300-1/LTC4300-2 provide bidirectional
buffering, keeping the backplane and card capacitances
isolated. Rise time accelerator circuitry* allows the use of
weaker DC pull-up currents while still meeting rise time
requirements. During insertion, the SDA and SCL lines are
precharged to 1V to minimize bus disturbances.
The LTC4300-1 incorporates a CMOS threshold digital
ENABLE input pin, which forces the part into a low current
mode when driven to ground and sets normal operation
when driven to V
CC
. It also includes an open drain READY
output pin, which indicates that the backplane and card
sides are connected together. The LTC4300-2 replaces
the ENABLE pin with a dedicated supply voltage pin, V
CC2
,
for the card side, providing level shifting between 3.3V
and 5V systems. Both the backplane and card may be
powered with supply voltages ranging from 2.7V to 5.5V,
with no constraints on which supply voltage is higher.
The LTC4300-2 also replaces the READY pin with a digital
CMOS input pin, ACC, which enables and disables the rise
time accelerator currents.
The LTC4300 is available in a small 8-lead MSOP package.
n
n
n
n
n
n
n
n
n
Bidirectional Buffer for SDA and SCL Lines
Increases Fanout
Prevents SDA and SCL Corruption During Live
Board Insertion and Removal From Backplane
Isolates Input SDA and SCL Lines From Output
Compatible with I
2
C, I
2
C Fast Mode and SMBus
Standards (Up to 400kHz Operation)
Low I
CC
Chip Disable: <1µA (LTC4300-1)
READY Open-Drain Output (LTC4300-1)
1V Precharge on All SDA and SCL Lines
Supports Clock Stretching, Arbitration and
Synchronization
5V to 3.3V Level Translation (LTC4300-2)
High Impedance SDA, SCL Pins for V
CC
= 0V
Small MSOP 8-Lead Package
applicaTions
n
n
n
n
Hot Board Insertion
Servers
Capacitance Buffer/Bus Extender
Desktop Computer
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners. *Protected by U.S. Patents, including 6650174.
Typical applicaTion
V
CC
3.3V
R1
24k
SCLIN
C2*
R2
24k
3
8
2
C1
0.01µF
R3
24k
R4
24k
SCLOUT
C4*
OUTPUT SIDE
50pF
0.5V/DIV
INPUT SIDE
150pF
Input–Output Connection t
PLH
SDAIN
C3*
6
7
C5*
LTC4300-1
5
ENABLE
READY
GND
4
SDAOUT
1
*CAPACITORS NOT REQUIRED
IF BUS IS SUFFICIENTLY LOADED
200ns/DIV
430012 TA01b
430012 TA01a
430012fb
For more information
www.linear.com/LTC4300-1
1
LTC4300-1/LTC4300-2
absoluTe maximum raTings
(Note 1)
pin conFiguraTion
TOP VIEW
ENABLE/V
CC2
*
SCLOUT
SCLIN
GND
1
2
3
4
8
7
6
5
V
CC
SDAOUT
SDAIN
READY/ACC*
V
CC
to GND ..................................................– 0.5V to 7V
V
CC2
to GND (LTC4300-2) ............................ –0.5V to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT................ –0.5V to 7V
READY, ENABLE (LTC4300-1) ...................... –0.5V to 7V
ACC (LTC4300-2) ......................................... –0.5V to 7V
Operating Temperature Range
LTC4300-1C/LTC4300-2C ........................ 0°C to 70°C
LTC4300-1I/LTC4300-2I ......................–40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec)................... 300°C
MS8 PACKAGE
8-LEAD PLASTIC MSOP
*LTC4300-2
T
JMAX
= 125°C,
θ
JA
= 200°C/W
orDer inFormaTion
LEAD FREE FINISH
LTC4300-1CMS8#PBF
LTC4300-1IMS8#PBF
LTC4300-2CMS8#PBF
LTC4300-2IMS8#PBF
TAPE AND REEL
LTC4300-1CMS8#TRPBF
LTC4300-1IMS8#TRPBF
LTC4300-2CMS8#TRPBF
LTC4300-2IMS8#TRPBF
PART MARKING*
LTUB
LTUC
LTVJ
LTVK
PACKAGE DESCRIPTION
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part markings, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 2.7V to 5.5V, unless otherwise noted.
SYMBOL
Power Supply
V
CC
I
CC
I
SD
V
CC2
I
VCC1
I
VCC2
Positive Supply Voltage
Supply Current
Supply Current in Shutdown Mode
Card Side Supply Voltage
V
CC
Supply Current
V
CC2
Supply Current
V
CC
= 5.5V, V
SDAIN
= V
SCLIN
= 0V, LTC4300-1
V
ENABLE
= 0V, LTC4300-1
LTC4300-2
V
SDAIN
= V
SCLIN
= 0V, V
CC1
= V
CC2
= 5.5V,
LTC4300-2
V
SDAOUT
= V
SCLOUT
= 0V, V
CC1
= V
CC2
= 5.5V,
LTC4300-2
SDA, SCL Floating
LTC4300-1
●
●
●
●
●
elecTrical characTerisTics
PARAMETER
CONDITIONS
MIN
2.7
TYP
MAX
5.5
UNITS
V
mA
µA
V
mA
mA
2.8
0.1
2.7
1.8
1.2
6
5.5
3.6
2.4
Start-Up Circuitry
V
PRE
t
IDLE
V
EN
Precharge Voltage
Bus Idle Time
ENABLE Threshold Voltage
0.8
50
1.0
95
0.5 • V
CC
1.2
150
0.9 • V
CC
V
µs
V
430012fb
2
For more information
www.linear.com/LTC4300-1
LTC4300-1/LTC4300-2
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 2.7V to 5.5V, V
CC2
= 2.7V to 5.5V, unless otherwise noted.
SYMBOL
V
DIS
I
EN
t
PHL
t
PLH
I
OFF
V
OL
I
PULLUPAC
PARAMETER
Disable Threshold Voltage
ENABLE Input Current
ENABLE Delay, On-Off
READY Delay, Off-On
ENABLE Delay, Off-On
READY Delay, On-Off
READY OFF State Leakage Current
READY Output Low Voltage
Transient Boosted Pull-Up Current
CONDITIONS
LTC4300-1, ENABLE Pin
ENABLE from 0V to V
CC
, LTC4300-1
LTC4300-1
LTC4300-1
LTC4300-1
LTC4300-1
LTC4300-1
I
PULLUP
= 3mA, LTC4300-1
Positive Transition on SDA, SCL, V
CC
= 2.7V,
Slew Rate = 1.25V/µs (Note 2),
LTC4300-2, ACC = 0.7 • V
CC2
, V
CC2
= 2.7V
LTC4300-2
LTC4300-2
LTC4300-2
LTC4300-2
10k to V
CC
on SDA, SCL, V
CC
= 3.3V (Note 3),
LTC4300-2, V
CC2
= 3.3V, V
IN
= 0.2V
Guaranteed by Design, Not Subject to Test
Guaranteed by Design, Not Subject to Test
SDA, SCL Pins, I
SINK
= 3mA, V
CC
= 2.7V,
V
CC2
= 2.7V, LTC4300-2
SDA, SCL Pins = V
CC
= 5.5V,
LTC4300-2, V
CC2
= 5.5V
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Notes 4, 5)
(Notes 4, 5)
LTC4300-1: V
CC
= 2.7V, V
CC
= 5.5V (Note 6)
LTC4300-2: V
CC
= 2.7V, V
CC2
= 5.5V;
V
CC
= 5.5V, V
CC2
= 2.7V (Note 6)
l
l
l
l
●
elecTrical characTerisTics
MIN
0.1 • V
CC
TYP
0.5 • V
CC
±0.1
100
10
80
10
±0.1
MAX
±1
UNITS
V
µA
ns
ns
µs
µs
µA
0.4
1
2
V
mA
Rise Time Accelerators
V
ACCDIS
V
ACCEN
I
VACC
t
PDOFF
V
OS
f
SCL, SDA
C
IN
V
OL
I
LEAK
Accelerator Disable Threshold
Accelerator Enable Threshold
ACC Input Current
ACC Delay, On/Off
Input-Output Offset Voltage
Operating Frequency
Digital Input Capacitance
Output Low Voltage, Input = 0V
Input Leakage Current
0.3 • V
CC2
0.5 • V
CC2
0.5 • V
CC2
0.7 • V
CC2
± 0.1
5
±1
V
V
µA
ns
150
400
10
0.4
±5
mV
kHz
pF
V
µA
Input-Output Connection
0
0
0
75
Timing Characteristics
f
I2C
t
BUF
t
hD,STA
t
su,STA
t
su,STO
t
hD, DAT
t
su, DAT
t
LOW
t
HIGH
t
f
t
r
t
PHL,SKEW
I
2
C Operating Frequency
Bus Free Time Between STOP and
START Condition
Hold Time After (Repeated) START
Condition
Repeated START Condition Setup
Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
Clock LOW Period
Clock HIGH Period
Clock, Data Fall Time
Clock, Data Rise Time
High-to-Low Propagation Delay
Skew, SCL-SDA
0
1.3
0.6
0.6
0.6
300
100
1.3
0.6
20 + 0.1 • C
B
20 + 0.1 • C
B
0
0
300
300
±75
±75
400
kHz
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
430012fb
For more information
www.linear.com/LTC4300-1
3
LTC4300-1/LTC4300-2
elecTrical characTerisTics
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
I
PULLUPAC
varies with temperature and V
CC
voltage, as shown in
the Typical Performance Characteristics section.
Note 3:
The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and V
CC
voltage is shown in the Typical Performance
Characteristics section.
Note 4:
Guaranteed by design, not subject to test.
Note 5:
C
B
= total capacitance of one bus line in pF.
Note 6:
These tests measure the difference in high-to-low propagation
delay t
PHL
between the clock and data channels. The delay on each
channel is measured from the 50% point of the falling driven input signal
to the 50% point of the output driven by the LTC4300-1/LTC4300-2.
The skew is defined as (t
PHL(SCL)
- t
PHL(SDA)
). Testing is performed in
both directions—from input bus to output bus and vice versa. Tests are
performed with approximately 500pF of distributed equivalent capacitance
on each SDA and SCL pin.
Typical perFormance characTerisTics
3.0
2.9
2.8
I
CC
(mA)
t
PHL
(ns)
2.7
2.6
2.5
2.4
2.3
2.2
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
430012 G01
I
CC
vs Temperature (LTC4300-1)
100
V
CC
= 5.5V
Input–Output t
PHL
vs Temperature
(LTC4300-1)
V
CC
= 2.7V
80
V
CC
= 3.3V
60
V
CC
= 2.7V
40
V
CC
= 5.5V
20
C
IN
= C
OUT
= 100pF
R
PULLUPIN
= R
PULLUPOUT
= 10k
–25
0
25
50
TEMPERATURE (°C)
75
100
430012 G02
0
–50
12
10
I
PULLUPAC
(mA)
8
6
4
2
I
PULLUPAC
vs Temperature
300
V
CC
= 5V
250
V
OUT
– V
IN
(mV)
200
150
100
50
0
Connection Circuitry V
OUT
– V
IN
T
A
= 25°C
V
IN
= 0V
V
CC
= 3V
V
CC
= 5V
V
CC
= 3.3V
0
10,000
20,000
30,000
R
PULLUP
( )
40,000
430012 G04
V
CC
= 2.7V
–25
0
25
50
TEMPERATURE (°C)
75
100
430012 G03
0
–50
4
430012fb
For more information
www.linear.com/LTC4300-1
LTC4300-1/LTC4300-2
pin FuncTions
ENABLE/V
CC2
(Pin 1):
Chip Enable Pin/Card Supply Volt-
age. For the LTC4300-1, this is a digital CMOS threshold
input pin. Grounding this pin puts the part in a low current
(<1µA) mode. It also disables the rise time accelerators,
disables the bus precharge circuitry, drives READY low,
isolates SDAIN from SDAOUT and isolates SCLIN from
SCLOUT. Drive ENABLE all the way to V
CC
for normal
operation. Connect ENABLE to V
CC
if this feature is not
being used. For the LTC4300-2, this is the supply voltage
for the devices on the card I
2
C busses. Connect pull-up
resistors from SDAOUT and SCLOUT to this pin. Place a
bypass capacitor of at least 0.01µF close to this pin for
best results.
SCLOUT (Pin 2):
Serial Clock Output. Connect this pin
to the SCL bus on the card. See Figures 3 and 4 for bus
pull-up resistance and capacitance requirements.
SCLIN (Pin 3):
Serial Clock Input. Connect this pin to the
SCL bus on the backplane. See Figures 3 and 4 for bus
pull-up resistance and capacitance requirements.
GND (Pin 4):
Ground. Connect this pin to a ground plane
for best results.
READY/ACC (Pin 5):
Connection Flag/Rise time Accel-
erator Control. For the LTC4300-1, this is an open-drain
NMOS output which pulls LOW when either ENABLE is
LOW or the start-up sequence described in the Operation
section has not been completed. READY goes HIGH when
ENABLE is HIGH and start-up is complete. Connect a 10k
resistor from this pin to V
CC
to provide the pull up. For
the LTC4300-2, this is a CMOS threshold digital input pin
that enables and disables the rise time accelerators on all
four SDA and SCL pins. Drive ACC all the way to the V
CC2
supply voltage to enable all four accelerators; drive ACC
to ground to turn them off.
SDAIN (Pin 6):
Serial Data Input. Connect this pin to the
SDA bus on the backplane. See Figures 3 and 4 for bus
pull-up resistance and capacitance requirements.
SDAOUT (Pin 7):
Serial Data Output. Connect this pin
to the SDA bus on the card. See Figures 3 and 4 for bus
pull-up resistance and capacitance requirements.
V
CC
(Pin 8):
Main Input Power Supply From Backplane.
This is the supply voltage for the devices on the backplane
I
2
C busses. Connect pull-up resistors from SDAIN and
SCLIN to this pin. Place a bypass capacitor of at least
0.01µF close to this pin for best results.
430012fb
For more information
www.linear.com/LTC4300-1
5
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