DEMO MANUAL DC1763A
LTC2195, LTC2194, LTC2193,
LTC2192, LTC2191, LTC2190, LTC2271
16-Bit, 20Msps to 125Msps Dual ADCs
Description
Demonstration circuit 1763A supports a family of 16-Bit
20Msps to 125Msps ADCs. Each assembly features one
of the following devices:
LTC
®
2195, LTC2194, LTC2193,
LTC2192, LTC2191, LTC2190, LTC2271
high speed, dual
ADCs.
The versions of the 1763A demo board are listed in Table 1.
Depending on the required resolution and sample rate,
Table 1. DC1763A Variants
DC1763A VARIANTS
1763A-A
1763A-B
1763A-C
1763A-D
1763A-E
1763A-F
1763A-G
ADC PART NUMBER
LTC2195
LTC2194
LTC2193
LTC2192
LTC2191
LTC2190
LTC2271
RESOLUTION
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
MAXIMUM SAMPLE RATE
125Msps
105Msps
80Msps
65Msps
40Msps
25Msps
20Msps
INPUT FREQUENCY
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
the DC1763A is supplied with the appropriate ADC. The
circuitry on the analog inputs is optimized for analog input
frequencies from 5MHz to 140MHz. Refer to the data sheet
for proper input networks for different input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo/DC1763A
L,
LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks
and PScope is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
perForMAnce sUMMArY
PARAMETER
Supply Voltage – DC1763A
Analog Input Range
Logic Input Voltages
Logic Output Voltages (Differential)
(T
A
= 25°C)
MIN
3
1
1.3
0.6
350
1.25
247
1.25
See Table 1
0
0.2
See Table 1
See Table 1
See Applicable Data Sheet
See Applicable Data Sheet
dc1763afb
CONDITIONS
Depending on Sampling Rate and the A/D Converter
Provided, this Supply Must Provide up to 500mA.
Depending on SENSE Pin Voltage
Minimum Logic High
Maximum Logic Low
Nominal Logic Levels (100Ω Load, 3.5mA Mode)
Common Mode
Minimum Logic Levels (100Ω Load, 3.5mA Mode)
Common Mode
Single-Ended Encode Mode (ENC
–
Tied to GND)
Differential Encode Mode (ENC
–
Not Tied to GND)
TYP
3.6
MAX
6
2
UNITS
V
V
P-P
V
V
mV
V
mV
V
Sampling Frequency (Convert Clock Frequency)
Encode Clock Level
Resolution
Input Frequency Range
SFDR
SNR
3.6
3.6
V
V
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DEMO MANUAL DC1763A
qUick stArt proceDUre
Demonstration circuit 1763A is easy to set up to evaluate
the performance of the LTC2195 A/D converter family. Refer
to Figure 1 for proper measurement equipment setup and
follow the procedure below:
Setup
If a DC1371 PStache Data Acquisition and Collection
System was supplied with the DC1763A demonstration
circuit, follow the DC1371 Quick Start Guide to install the
required software and for connecting the DC1371 to the
DC1763A and to a PC.
DC1763A Demonstration Circuit Board Jumpers
The DC1763 demonstration circuit board should have
the following jumper settings as default positions: (as
per Figure 1)
JP13: PAR/SER : Selects parallel or serial programming
mode. (Default: serial)
Optional Jumpers:
JP5: ILVDS: Selects either 1.75mA or 3.5mA of output
current for the LVDS drivers. (Default: 3.5mA)
JP15: SHDN: Enables and disables the LTC2195. (De-
fault: SHDN)
JP2: WP: Enable/Disables write protect for the EEPROM.
(Default: EN)
JP14/JP8: LANE/TERM: Two bits that select between
one, two and four lanes.
JP14 – LANE
2
2
1
1
JP8 TERM
DIS
EN
DIS
EN
NUMBER OF LANES
2
4
1
Not Used
(Default: JP8: EN, JP14: 1)
3V TO 6V
TO PROVIDED
POWER SUPPLY
ANALOG INPUTS
CHANNEL 1
TO PROVIDED
USB CABLE
CHANNEL 2
dc1763a F01
PARALLEL/SERIAL
SINGLE-ENDED
ENCODE CLOCK
(USE PROVIDED DC1075,
DIVIDE BY 4-CLOCK BOARD)
Figure 1. Demo Board Setup
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DEMO MANUAL DC1763A
qUick stArt proceDUre
Notes:
1. The DC1371 does not support 1- or 4-lane operation.
2. Optional jumper should be left open to ensure proper
serial configuration.
3. In the first revision of this demo board the jumpers
were mislabeled. For boards labeled with a Rev 1 use
the following jumper positions:
a. JP8: Term: Selects either 1.75mA or 3.5mA of output
current for the LVDS drivers. (Default: 3.5mA)
b. JP14/JP5: ILVDS/LANE: Two bits that select between
one, two and four lanes.
JP14 – ILVDS
3.5mA
3.5mA
1.75mA
1.75mA
JP5 LANE
2
1
2
1
NUMBER OF LANES
2
1
4
Not Used
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a gallium arsenide gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Apply the analog input signal of interest to the SMA con-
nectors on the DC1763A demonstration circuit board
marked J3 AIN1 and J4 AIN2. These inputs correspond
with channels one and two of the ADC respectively. These
inputs are capacitively coupled to balun transformers
ETC1-1-13 (lead free part number MABA007159-000000).
Encode Clock
NOTE: Apply an encode clock to the SMA connector on
the DC1763A demonstration circuit board marked J12
CLK
+
. As a default the DC1763A is populated to have a
single-ended input.
For the best noise performance, the encode clock must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
P-P
or 13dBm. When
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075 that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2195. Using band pass filters on the clock and
the analog input will improve the noise performance by
reducing the wideband noise power of the signals. In
the case of the DC1763A a band pass filter used for the
clock should be used prior to the DC1075. Data sheet FFT
plots are taken with 10-pole LC filters made by TTE (Los
Angeles, CA) to suppress signal generator harmonics,
non-harmonically related spurs and broadband noise.
Low phase noise Agilent 8644B generators are used for
both the clock input and the analog input.
dc1763afb
Applying Power and Signals to the DC1763A
Demonstration Circuit
If a DC1371 is used to acquire data from the DC1763A, the
DC1371 must FIRST be connected to a powered USB port
and have 5V applied BEFORE applying 3.0V to 6V across
the pins marked V
+
and GND on the DC1763A. DC1763A
requires 3.6V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1763A demonstration circuit requires up
to 500mA depending on the sampling rate and the A/D
converter supplied.
The DC1763A should not be removed, or connected to
the DC1371 while power is applied.
Analog Input Network
For optimal distortion and noise performance the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen-
cies above 140MHz, refer to the LTC2195 data sheet for a
proper input network. Other input networks may be more
appropriate for input frequencies less that 5MHz.
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR.
3
DEMO MANUAL DC1763A
qUick stArt proceDUre
Digital Outputs
The data outputs, data clock, and frame clock signals are
available on J1 of the DC1763A. This connector follows the
VITA-57/FMC standard, but all signals should be verified
when using an FMC carrier card other than the DC1371.
Software
The DC1371 is controlled by the PScope™ System Soft-
ware provided or downloaded from the Linear Technology
website at http://www.linear.com/software/.
To start the data collection software if PScope.exe, is in-
stalled (by default) in \Program Files\LTC\PScope\, double
click the PScope icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC1763A demonstration circuit is properly connected
to the DC1371, PScope should automatically detect the
DC1763A, and configure itself accordingly. If everything is
hooked up properly, powered and a suitable convert clock
is present, clicking the Collect button should result in time
and frequency plots displayed in the PScope window. Ad-
ditional information and help for PScope is available in the
DC1371 Quick Start Guide and in the online help available
within the PScope program itself.
Serial Programming
PScope has the ability to program the DC1763A board
serially through the DC1371. There are several options
available in the LTC2195 family that are only available
through serially programming. PScope allows all of these
features to be tested.
These options are available by first clicking on the Set
Demo Bd Options icon on the PScope toolbar (Figure 2).
This will bring up the menu shown in Figure 3.
Figure 3. Demobd Configuration Options
Figure 2. PScope Toolbar
dc1763afb
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DEMO MANUAL DC1763A
qUick stArt proceDUre
This menu allows any of the options available for the
LTC2195 family to be programmed serially. The LTC2195
family has the following options:
Randomizer:
Enables data output randomizer
• Off (Default): Disables data output randomizer
• On: Enables data output randomizer
Two’s Complement:
Enables two’s complement mode
• Off (Default): Selects offset binary mode
• On: Selects two’s complement mode
Sleep Mode:
Selects between normal operation, sleep
mode:
• Off (Default): Entire ADC is powered, and active
• On: The entire ADC is powered down.
Channel 1 Nap:
Selects between normal operation and
putting channel 1 in nap mode.
• Off (Default): Channel one is active
• On: Channel one is in nap mode
Channel 2 Nap:
Selects between normal operation and
putting channel 2 in nap mode.
• Off (Default): Channel two is active
• On: Channel two is in nap mode
Output Current:
Selects the LVDS output drive current
• 1.75mA (Default): LVDS output driver current
• 2.1mA: LVDS output driver current
• 2.5mA: LVDS output driver current
• 3.0mA: LVDS output driver current
• 3.5mA: LVDS output driver current
• 4.0mA: LVDS output driver current
• 4.5mA: LVDS output driver current
Internal Termination:
Enables LVDS internal termination
• Off (Default): Disables internal termination
• On: Enables internal termination
Outputs:
Enables digital outputs
• Enabled (Default): Enables digital outputs
• Disabled: Disables digital outputs
Test Pattern:
Selects digital output test patterns. The
desired test pattern can be entered into the text boxes
provided.
• Off (Default): ADC input data is displayed
• On: Test pattern is displayed.
Once the desired settings are selected hit OK and PScope
will automatically update the register of the device on the
DC1763A demo board.
dc1763afb
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