4M
×
1-Bit Dynamic RAM
HYB 514100BJ-50/-60
Advanced Information
• 4 194 304 words by 1-bit organization
• 0 to 70
°C
operating temperature
• Fast Page Mode Operation
• Performance:
-50
-60
60
15
30
110
40
ns
ns
ns
ns
ns
t
RAC
RAS access time
t
CAC
CAS access time
t
AA
t
RC
t
PC
Access time from address
Read/Write cycle time
Fast page mode cycle time
50
13
25
95
35
• Single + 5 V (± 10 %) supply with a built-in
V
BB
generator
• Low power dissipation
max. 660 mW active (-50 version)
max. 605 mW active (-60 version)
• Standby power dissipation:
11 mW max. standby (TTL)
5.5 mW max. standby (CMOS)
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh,
hidden refresh and test mode capability
• All inputs and outputs TTL-compatible
• 1024 refresh cycles/16 ms
• Plastic Packages: P-SOJ-26/20-2 with 300 mil width
Semiconductor Group
1
1998-10-01
HYB 514100BJ-50/-60
4M
×
1 DRAM
The HYB 514100BJ is the new generation dynamic RAM organized as 4 194 304 words by 1-bit.
The HYB 514100BJ utilizes CMOS silicon gate process as well as advances circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 514100BJ to be packed in a standard plastic P-SOJ-26/20 package. This package
size provides high system bit densities and is compatible with commonly used automatic testing and
insertion equipment. System oriented features include single + 5 V (± 10 %) power supply, direct
interfacing with high performance logic device families such as Schottky TTL.
Type
HYB 514100BJ-50
HYB 514100BJ-60
Ordering Code
Q67100-Q971
Q67100-Q759
Package
P-SOJ-26/20-2 300 mil
P-SOJ-26/20-2 300 mil
Descriptions
DRAM (access time 50 ns)
DRAM (access time 60 ns)
P-SOJ-26/20-2
V
SS
DO
CAS
N.C.
A9
DI
WE
RAS
N.C.
A10
1
2
3
4
5
26
25
24
23
22
A0
A1
A2
A3
V
CC
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
SPP02808
Pin Configuration
Pin Names
A0 – A10
RAS
CAS
WE
DI
DO
Address Input
Row Address Strobe
Column Address Strobe
Read/Write Input
Data In
Data Out
Power Supply (+ 5 V)
Ground (0 V)
No Connection
V
CC
V
SS
N.C.
Semiconductor Group
2
1998-10-01
HYB 514100BJ-50/-60
4M
×
1 DRAM
WE
CAS
&
Data In
Buffer
DI
No.2 Clock
Generator
Data Out
Buffer
DO
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
11
Column
Address
Buffers (11)
11
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
Refresh
Counter (10)
10
Row
Address
Buffers (11)
10
Row
Decoder
.
.
.
1024
.
.
.
4096
Memory Array
.
.
.
.
.
.
RAS
No.1 Clock
Generator
Substrate Bias
Generator
V
CC
V
SS
SPB02847
Block Diagram
Semiconductor Group
3
1998-10-01
HYB 514100BJ-50/-60
4M
×
1 DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................... 0 to 70
°C
Storage temperature range.................................................................................... – 55 to + 150
°C
Input/output voltage ....................................................................................................... – 1 to + 7 V
Power Supply voltage .................................................................................................... – 1 to + 7 V
Data out current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
T
A
= 0 to 70
°C,
V
SS
= 0 V,
V
CC
= 5 10 %,
t
T
= 5 ns
Parameter
Input high voltage
Input low voltage
Output high voltage (
I
OUT
= – 5 mA)
Output low voltage (
I
OUT
= 4.2 mA)
Input leakage current, any input
(0 V <
V
IN
< 7, all other input = 0 V)
Output leakage current
(DO is disabled, 0 <
V
OUT
<
V
CC
)
Average
V
CC
supply current
-50 version
-60 version
Standby
V
CC
supply current
(RAS = CAS = WE =
V
IH
)
Symbol
Limit Values
min.
max.
0.8
–
0.4
10
10
2.4
– 1.0
2.4
–
– 10
– 10
Unit Test
Condition
1
1
1
1
1
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
V
CC
+ 0.5 V
V
V
V
µA
µA
1
–
–
120
110
2
mA
mA
mA
2, 3
I
CC2
–
Average
V
CC
supply current during RAS-only
I
CC3
refresh cycles
-50 version
-60 version
Average
V
CC
supply current during fast page
I
CC4
mode operation
-50 version
-60 version
–
–
120
110
mA
mA
2
–
–
80
70
mA
mA
2, 3
Semiconductor Group
4
1998-10-01
HYB 514100BJ-50/-60
4M
×
1 DRAM
DC Characteristics
(cont’d)
T
A
= 0 to 70
°C,
V
SS
= 0 V,
V
CC
= 5 10 %,
t
T
= 5 ns
Parameter
Standby
V
CC
supply current
Average
V
CC
supply current during
CAS-before-RAS refresh mode
-50 version
-60 version
Capacitance
T
A
= 0 to 70
°C,
V
CC
= 5.0 V
± 10 %,
f
= 1 MHz
Parameter
Input capacitance (A0 to A10, DI)
Input capacitance (RAS, CAS, WE)
Output capacitance (DO)
AC Characteristics
5, 6
T
A
= 0 to 70
°C,
V
CC
= 5 V
± 10 %,
t
T
= 5 ns
Parameter
Symbol
Limit Values
-50
min. max.
Common Parameters
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
CAS hold time
-60
min. max.
Unit Note
Symbol
Limit Values
min.
max.
5
7
7
pF
pF
pF
–
–
–
Unit
Symbol
Limit Values
min.
max.
1
–
Unit Test
Condition
mA
1
2
I
CC5
I
CC6
–
–
120
110
mA
mA
C
I1
C
I2
C
IO
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
5
95
35
50
13
0
8
0
10
18
13
13
50
–
–
10k
10k
–
–
–
–
37
25
110
40
60
15
0
10
0
15
20
15
15
60
–
–
10k
10k
–
–
–
–
45
30
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Semiconductor Group
1998-10-01
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