74HC03D
CMOS Digital Integrated Circuits Silicon Monolithic
74HC03D
1. Functional Description
•
Quad 2-Input NAND Gate (Open Drain)
2. General
The 74HC03D is a high speed CMOS 2-INPUT NAND GATE fabricated with silicon gate C
2
MOS technology.
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power
dissipation.
Pin configuration and function are the same as the 74HC00D. But the 74HC03D has, as its outputs, high
performance MOS N-channel transistors. (open-drain outputs) This device can, thefore, with a suitable pull-up
resistors, be used in wired-AND, LED driver and other application.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
3. Features
(1)
(2)
(3)
(4)
High speed: t
pz
= 5 ns (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 1.0
µA
(max) at T
a
= 25
Wide operating voltage range: V
CC(opr)
= 2.0 to 6.0 V
Open drain structure
4. Packaging
SOIC14
Start of commercial production
©2016 Toshiba Corporation
1
2016-05
2016-08-04
Rev.3.0
74HC03D
5. Pin Assignment
6. Marking
7. IEC Logic Symbol
©2016 Toshiba Corporation
2
2016-08-04
Rev.3.0
74HC03D
8. Truth Table
A
L
L
H
H
B
L
H
L
H
Y
Z
Z
Z
L
Z:
High impedance
9. System Diagram (per gate)
10. Absolute Maximum Ratings (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Input diode current
Output diode current
Output current
V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
(Note 1)
Note
Rating
-0.5 to 7.0
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±20
±20
±25
±50
500
-65 to 150
Unit
V
V
V
mA
mA
mA
mA
mW
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note 1: PD derates linearly with -8 mW/ above 85
11. Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise and fall times
Symbol
V
CC
V
IN
V
OUT
T
opr
t
r
,t
f
Test Condition
Rating
2.0 to 6.0
0 to V
CC
0 to V
CC
-40 to 125
0 to 50
Unit
V
V
V
µs
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs and bus inputs must be tied to either V
CC
or GND.
©2016 Toshiba Corporation
3
2016-08-04
Rev.3.0
74HC03D
12. Electrical Characteristics
12.1. DC Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
High-level input voltage
Symbol
V
IH
Test Condition
V
CC
(V)
2.0
4.5
6.0
Low-level input voltage
V
IL
2.0
4.5
6.0
Low-level output voltage
V
OL
V
IN
= V
IH
or V
IL
I
OL
= 20
µA
2.0
4.5
6.0
I
OL
= 4 mA
I
OL
= 5.2 mA
Output OFF-state leakage
current
Input leakage current
Quiescent supply current
I
OZ
I
IN
I
CC
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
V
IN
= V
CC
or GND
V
IN
= V
CC
or GND
4.5
6.0
6.0
6.0
6.0
Min
1.50
3.15
4.20
Typ.
0.0
0.0
0.0
0.17
0.18
Max
0.50
1.35
1.80
0.1
0.1
0.1
0.26
0.26
±0.5
±0.1
1.0
µA
µA
µA
V
V
Unit
V
12.2. DC Characteristics (Unless otherwise specified, T
a
= -40 to 85
)
Characteristics
High-level input voltage
Symbol
V
IH
Test Condition
V
CC
(V)
2.0
4.5
6.0
Low-level input voltage
V
IL
2.0
4.5
6.0
Low-level output voltage
V
OL
V
IN
= V
IH
or V
IL
I
OL
= 20
µA
2.0
4.5
6.0
I
OL
= 4 mA
I
OL
= 5.2 mA
Output OFF-state leakage
current
Input leakage current
Quiescent supply current
I
OZ
I
IN
I
CC
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
V
IN
= V
CC
or GND
V
IN
= V
CC
or GND
4.5
6.0
6.0
6.0
6.0
Min
1.50
3.15
4.20
Max
0.50
1.35
1.80
0.1
0.1
0.1
0.33
0.33
±5.0
±1.0
10.0
µA
µA
µA
V
V
Unit
V
©2016 Toshiba Corporation
4
2016-08-04
Rev.3.0
74HC03D
12.3. DC Characteristics (Unless otherwise specified, T
a
= -40 to 125
)
Characteristics
High-level input voltage
Symbol
V
IH
Test Condition
V
CC
(V)
2.0
4.5
6.0
Low-level input voltage
V
IL
2.0
4.5
6.0
Low-level output voltage
V
OL
V
IN
= V
IH
or V
IL
I
OL
= 20
µA
2.0
4.5
6.0
I
OL
= 4 mA
I
OL
= 5.2 mA
Output OFF-state leakage
current
Input leakage current
Quiescent supply current
I
OZ
I
IN
I
CC
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
V
IN
= V
CC
or GND
V
IN
= V
CC
or GND
4.5
6.0
6.0
6.0
6.0
Min
1.50
3.15
4.20
Max
0.50
1.35
1.80
0.1
0.1
0.1
0.4
0.4
±10.0
±1.0
40.0
µA
µA
µA
V
V
Unit
V
12.4. AC Characteristics
(Unless otherwise specified, C
L
=15 pF, V
CC
= 5 V, T
a
= 25
, Input: t
r
= t
f
= 6 ns)
Characteristics
Output transition time
Propagation delay time
Symbol
t
TLH
,t
THL
t
PLZ
t
PZL
Test Condition
R
L
= 1 kΩ
Min
Typ.
4
5
5
Max
8
12
12
Unit
ns
ns
12.5. AC Characteristics (Unless otherwise specified, C
L
=50 pF, T
a
= 25
, Input: t
r
= t
f
= 6 ns)
Characteristics
Output transition time
Symbol
t
TLH
,t
THL
Note
Test
Condition
V
CC
(V)
2.0
4.5
6.0
Propagation delay time
t
PLZ
R
L
= 1kΩ
2.0
4.5
6.0
Propagation delay time
t
PZL
R
L
= 1kΩ
2.0
4.5
6.0
Input capacitance
Output capacitance
Power dissipation capacitance
C
IN
C
OUT
C
PD
(Note 1)
Min
Typ.
30
8
7
20
10
9
24
8
7
3
4
3
Max
75
15
13
75
15
13
75
15
13
pF
pF
pF
ns
ns
Unit
ns
Note 1: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load. Average operating current can be obtained by the equation.
I
CC(opr)
= C
PD
×
V
CC
×
f
IN
+ I
CC
/4 (per gate)
©2016 Toshiba Corporation
5
2016-08-04
Rev.3.0
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