PRMH9
50 V, 100 mA NPN/NPN Resistor-Equipped double Transistors
(RET)
14 September 2018
Product data sheet
1. General description
NPN/NPN Resistor-Equipped double Transistors (RET) in a leadless ultra small DFN1412-6
(SOT1268) Surface-Mounted Device (SMD) plastic package.
2. Features and benefits
•
•
•
•
•
•
•
100 mA output current capability
Built-in bias resistors
Simplifies circuit design
Reduces component count
Reduces pick and place costs
Low package height of 0.5 mm
AEC-Q101 qualified
3. Applications
•
•
•
•
Digital applications
Cost-saving alternative to BC847/BC857 series in digital applications
Control of IC inputs
Switching loads
4. Quick reference data
Table 1. Quick reference data
Symbol
Parameter
Per transistor
V
CEO
I
O
R1
R2/R1
[1]
Conditions
open base
Min
-
-
Typ
-
-
10
4.7
Max
50
100
13
5.7
Unit
V
mA
kΩ
collector-emitter
voltage
output current
bias resistor 1
bias resistor ratio
T
amb
= 25 °C
[1]
[1]
7
3.7
See section "Test information" for resistor calculation and test conditions.
Nexperia
PRMH9
50 V, 100 mA NPN/NPN Resistor-Equipped double Transistors (RET)
5. Pinning information
Table 2. Pinning information
Pin
Symbol Description
1
2
3
4
5
6
7
8
GND1
I1
O2
GND2
I2
O1
O1
O2
GND (emitter) TR1
input (base) TR1
output (collector) TR2
GND (emitter) TR2
input (base) TR2
output (collector) TR1
output (collector) TR1
output (collector) TR2
Transparent top view
1
2
3
8
7
6
5
4
TR1
R2
R1
R2
TR2
R1
Simplified outline
Graphic symbol
O1
I2
GND2
DFN1412-6
(SOT1268)
GND1
I1
O2
aaa-019894
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
PRMH9
DFN1412-6
Description
plastic thermal enhanced ultra thin small outline package; no
leads; 6 terminals; body: 1.4 mm x 1.2 mm x 0.47 mm
Version
SOT1268
7. Marking
Table 4. Marking codes
Type number
PRMH9
Marking code
B8
PRMH9
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
2 / 13
Nexperia
PRMH9
50 V, 100 mA NPN/NPN Resistor-Equipped double Transistors (RET)
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Per transistor
V
CBO
V
CEO
V
EBO
V
I
I
O
P
tot
Per device
P
tot
T
j
T
amb
T
stg
[1]
Parameter
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage
output current
total power dissipation
total power dissipation
junction temperature
ambient temperature
storage temperature
Conditions
open emitter
open base
open collector
positive
negative
T
amb
≤ 25 °C
T
amb
≤ 25 °C
[1]
[1]
Min
-
-
-
-
-
-
-
-
-
-55
-65
Max
50
50
6
40
-6
100
325
480
150
150
150
Unit
V
V
V
V
V
mA
mW
mW
°C
°C
°C
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.
500
P
tot
(mW)
400
aaa-024487
300
200
100
0
-75
-25
25
75
125
175
T
amb
(°C)
FR4 PCB, standard footprint
Fig. 1.
Per device: Power derating curve
PRMH9
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
3 / 13
Nexperia
PRMH9
50 V, 100 mA NPN/NPN Resistor-Equipped double Transistors (RET)
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
Parameter
Per transistor
R
th(j-a)
Per device
R
th(j-a)
[1]
Conditions
[1]
Min
-
Typ
-
Max
385
Unit
K/W
thermal resistance from in free air
junction to ambient
thermal resistance from in free air
junction to ambient
[1]
-
-
261
K/W
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
10
3
Z
th(j-a)
(K/W)
10
2
duty cycle = 1
0.75
0.33
0.1
0.05
10
0.02
0
0.01
0.5
0.2
aaa-024488
1
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, standard footprint
Fig. 2.
Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
PRMH9
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
4 / 13
Nexperia
PRMH9
50 V, 100 mA NPN/NPN Resistor-Equipped double Transistors (RET)
10. Characteristics
Table 7. Characteristics
Symbol
Parameter
Per transistor
I
CEO
I
CBO
I
EBO
h
FE
V
CEsat
V
I(off)
V
I(on)
R1
R2/R1
C
C
f
T
[1]
[2]
Conditions
Min
-
-
-
-
100
-
-
1.4
[1]
[1]
7
3.7
-
[2]
-
Typ
-
-
-
-
-
-
0.7
0.8
10
4.7
-
230
Max
1
5
100
150
-
100
0.5
-
13
5.7
2.5
-
Unit
µA
µA
nA
µA
collector-emitter cut-off V
CE
= 30 V; I
B
= 0 A; T
amb
= 25 °C
current
V
CE
= 30 V; I
B
= 0 A; T
amb
= 150 °C
collector-base cut-off
current
emitter-base cut-off
current
DC current gain
collector-emitter
saturation voltage
off-state input voltage
on-state input voltage
bias resistor 1
bias resistor ratio
collector capacitance
transition frequency
V
CB
= 10 V; I
E
= 0 A; i
e
= 0 A; f = 1 MHz;
T
amb
= 25 °C
V
CE
= 5 V; I
C
= 10 mA; f = 100 MHz;
T
amb
= 25 °C
V
CB
= 50 V; I
E
= 0 A; T
amb
= 25 °C
V
EB
= 5 V; I
C
= 0 A; T
amb
= 25 °C
V
CE
= 5 V; I
C
= 5 mA; T
amb
= 25 °C
I
C
= 5 mA; I
B
= 0.25 mA; T
amb
= 25 °C
V
CE
= 5 V; I
C
= 100 µA; T
amb
= 25 °C
V
CE
= 0.3 V; I
C
= 1 mA; T
amb
= 25 °C
T
amb
= 25 °C
mV
V
V
kΩ
pF
MHz
See section "Test information" for resistor calculation and test conditions.
Characteristics of built-in transistor
10
3
h
FE
(3)
006aac784
0.1
I
C
(A)
0.08
aaa-018582
0.50 mA
0.45 mA
0.40 mA
0.35 mA
0.30 mA
(1)
(2)
10
2
0.06
0.25 mA
0.20 mA
0.04
10
0.02
0.15 mA
0.10 mA
I
B
= 0.05 mA
1
10
-1
1
10
I
C
(mA)
10
2
0
0
1
2
3
4
V
CE
(V)
5
V
CE
= 5 V
(1) T
amb
= 100 °C
(2) T
amb
= 25 °C
(3) T
amb
= -40 °C
Fig. 3.
DC current gain as a function of collector
current; typical values
T
amb
= 25 °C
Fig. 4.
Collector current as a function of collector-
emitter voltage; typical values
PRMH9
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
5 / 13
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