Datasheet
Serial EEPROM series Standard EEPROM
MicroWire BUS EEPROM (3-Wire)
BR93G56-3A
General Description
BR93G56-3A is serial EEPROM of Serial 3-Line Interface Method.
They are 16bit organization and CS PIN is the first PIN in their PIN configuration.
Features
■
3-Line Communications of chip select, serial clock,
serial data input / output (the case where input and
output are shared)
■
Operations available at High Speed 3MHz clock
(4.5V to 5.5V)
■
High Speed Write available (write time 5ms max）
■
Same package and pin configuration from 1Kbit to
16Kbit
■
1.7V to 5.5V Single Power Source Operation
■
Address Auto Increment function at Read Operation
■
Write Error Prevention Function
» Write Prohibition at Power On
» Write Prohibition by Command Code
» Write Error Prevention function at Low Voltage
■
Self-timed Programming Cycle
■
Program Condition Display by READY / BUSY
■
Compact Package
SOP8 SOP-J8 SSOP-B8 TSSOP-B8 MSOP8
TSSOP-B8J DIP-T8 VSON008X2030
■
More than 40 years data retention
■
More than 1 million write cycles
■
Initial delivery state all addresses FFFFh (X16)
Packages
W(Typ) x D(Typ)x H(Max)
DIP-T8
9.30mm x 6.50mm x 7.10mm
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
SOP8
5.00mm x 6.20mm x 1.71mm
TSSOP-B8J
3.00mm x 4.90mm x 1.10mm
SOP- J8
4.90mm x 6.00mm x 1.65mm
MSOP8
2.90mm x 4.00mm x 0.90mm
SSOP-B8
3.00mm x 6.40mm x 1.35mm
VSON008X2030
2.00mm x 3.00mm x 0.60mm
BR93G56-3A
Capacity
2Kbit
Bit Format
128×16
Type
BR93G56-3A
Power Source
DIP-T8
(1)
Voltage
1.7V
to
5.5V
●
SOP8
SOP-J8
SSOP-B8
TSSOP-B8 TSSOP-B8J MSOP8
VSON008
X2030
●
●
●
●
●
●
●
(1) DIP-T8 is not halogen free package
○Product
structure：Silicon monolithic integrated circuit
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© 2013 ROHM Co., Ltd. All rights reserved.
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○This
product has no designed protection against radioactive rays
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BR93G56-3A
Absolute Maximum Ratings
Parameter
Supply Voltage
Symbol
Vcc
Rating
-0.3 to +6.5
800 (DIP-T8)
450 (SOP8)
450 (SOP-J8)
Permissible
Dissipation
Pd
300 (SSOP-B8)
330 (TSSOP-B8)
310 (TSSOP-B8J)
310 (MSOP8)
300 (VSON008X2030)
Storage
Temperature
Operating
Temperature
Input Voltage/
Output Voltage
Junction
Temperature
Tstg
Topr
‐
Tjmax
-65 to +150
-40 to +85
-0.3 to Vcc+1.0
150
℃
℃
V
℃
mW
Unit
V
Remark
Datasheet
Derate by 8.0mW/°C when operating above Ta=25°C
Derate by 4.5mW/°C when operating above Ta=25°C
Derate by 4.5mW/°C when operating above Ta=25°C
Derate by 3.0mW/°C when operating above Ta=25°C
Derate by 3.3mW/°C when operating above Ta=25°C
Derate by 3.1mW/°C when operating above Ta=25°C
Derate by 3.1mW/°C when operating above Ta=25°C
Derate by 3.0mW/°C when operating above Ta=25°C
The Max value of Input Voltage/Output Voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of Input
Voltage/Output Voltage is not under -0.8V.
Junction temperature at the storage condition
Memory Cell Characteristics (Vcc=1.7V to 5.5V)
Limit
Parameter
Min
Write Cycles
(1)
Data Retention
(1)
○Initial
data in all addresses are FFFFh(X16) upon delivery.
(1) Not 100% TESTED
Unit
Typ
-
-
Max
-
-
Times
Years
Conditions
1,000,000
40
Ta=25℃
Ta=25℃
Recommended Operating Ratings
Parameter
Supply Voltage
Input Voltage
Symbol
V
CC
V
IN
Limit
1.7 to 5.5
V
Unit
0 to V
CC
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BR93G56-3A
DC Characteristics
(Unless otherwise specified, Vcc=1.7V to 5.5V, Ta=-40℃ to +85℃)
Limit
Parameter
Symbol
Min
Input Low Voltage
Input High Voltage
Output Low Voltage 1
Output Low Voltage 2
Output High Voltage 1
Output High Voltage 2
Input Leakage
Current1
Output Leakage
Current
V
IL
V
IH
V
OL1
V
OL2
V
OH1
V
OH2
I
LI1
I
LO
-0.3
(1)
0.7Vcc
0
0
2.4
Vcc-0.2
-1
-1
-
I
CC1
-
-
Supply Current
I
CC2
-
-
I
CC3
-
Standby Current
I
SB1
-
-
-
3.0
2.0
mA
µA
-
-
1.0
2.0
mA
mA
f
SK
=3MHz (READ)
Vcc=2.5V, f
SK
=1MHz
t
E/W
=5ms (WRAL, ERAL)
Vcc=5.5V ,f
SK
=3MHz
t
E/W
=5ms (WRAL, ERAL)
CS=0V
-
-
2.0
0.5
mA
mA
Typ
-
-
-
-
-
-
-
-
-
Max
0.3Vcc
Vcc+1.0
0.4
0.2
Vcc
Vcc
+1
+1
1.0
V
V
V
V
V
V
µA
µA
mA
1.7V≦Vcc≦5.5V
1.7V≦Vcc≦5.5V
I
OL
=2.1mA, 2.7V≦Vcc≦5.5V
I
OL
=100μA
Unit
Conditions
Datasheet
I
OH
=-0.4mA, 2.7V≦Vcc≦5.5V
I
OH
=-100μA
V
IN
=0V to Vcc(CS,SK,DI)
V
OUT
=0V to Vcc, CS=0V
Vcc=1.7V, f
SK
=1MHz, t
E/W
=5ms (WRITE)
Vcc=5.5V ,f
SK
=3MHz, t
E/W
=5ms (WRITE)
f
SK
=1MHz (READ)
(1) When the pulse width is 50ns or less, the Min value of V
IL
is admissible to -0.8V.
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BR93G56-3A
AC Characteristics
(Unless otherwise specified, Vcc=1.7V to 2.5V, Ta=-40℃ to +85℃)
Parameter
SK Frequency
SK High Time
SK Low Time
CS Low Time
CS Setup Time
DI Setup Time
CS Hold Time
DI Hold Time
Data “1” Output Delay
Data “0” Output Delay
Time from CS to Output Establishment
Time from CS to High-Z
Write Cycle Time
Symbol
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
E/W
Limit
Min
-
250
250
250
200
100
0
100
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
1
-
-
-
-
-
-
-
400
400
400
200
5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Datasheet
(Unless otherwise specified, Vcc=2.5V to 4.5V, Ta=-40℃ to +85℃)
Parameter
SK Frequency
SK High Time
SK Low Time
CS Low Time
CS Setup Time
DI Setup Time
CS Hold Time
DI Hold Time
Data “1” Output Delay
Data “0” Output Delay
Time from CS to Output Establishment
Time from CS to High-Z
Write Cycle Time
Symbol
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
E/W
Limit
Min
-
230
200
200
50
100
0
100
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
2
-
-
-
-
-
-
-
200
200
150
100
5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
(Unless otherwise specified, Vcc=4.5V to 5.5V, Ta=-40℃ to +85℃)
Parameter
SK Frequency
SK High Time
SK Low Time
CS Low Time
CS Setup Time
DI Setup Time
CS Hold Time
DI Hold Time
Data “1” Output Delay
Data “0” Output Delay
Time from CS to Output Establishment
Time from CS to High-Z
Write Cycle Time
Symbol
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
E/W
Limit
Min
-
100
100
200
50
50
0
50
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
3
-
-
-
-
-
-
-
200
200
150
100
5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
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BR93G56-3A
Serial Input / Output Timing
Datasheet
CS
t
CSS
1/ f
SK
t
SKH
t
SKL
t
CSH
SK
t
DIS
t
D IH
DI
t
PD0
t
PD1
DO(READ)
t
SV
t
DF
DO(WRITE)
STATUS VALID
Figure 1. Serial Input / Output Timing
1.
2.
3.
4.
5.
6.
7.
Data is taken by DI sync with the rise of SK.
At read operation, data is output from DO in sync with the rise of SK.
The STATUS signal at write (READY / BUSY) is output after t
CS
from the fall of CS after write command input, at the area
DO where CS is high, and valid until the next command start bit is input. And, while CS is low, DO becomes High-Z.
After completion of each mode execution, set CS low once for internal circuit reset, and execute the following operation
mode.
1/f
SK
is the SK clock cycle, even if f
SK
is maximum, the SK clock cycle can’t be t
SKH
(Min)+t
SKL
(Min)
For “Write cycle time t
E/W
”, please see Figure 36,37,39,40.
For “CS low time t
CS
”, please see Figure 36,37,39,40.
Block Diagram
CS
Command Decode
Control
Power Source Voltage
SK
Clock Generation
Write
Prohibition
Address
Buffer
7bit
High Voltage Occurrence
DI
Command
Register
Address
Decoder
7bit
2,048 bit
EEPROM
Data
DO
Dummy Bit
Register
16bit
R/W
Amplifier
16bit
Figure 2. Block Diagram
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