Preliminary
◆CMOS
Voltage Detector
◆Manual
Reset Input
◆Watchdog
Functions
◆Built-in
Delay Circuit
◆Detect
Voltage Range: 1.6~5.0V, ± 2%
◆Reset
Function is Selectable
V
DFL
(Low When Detected)
V
DFH
(High When Detected)
■APPLICATIONS
●Microprocessor
reset circuits
●Memory
battery backup circuits
●System
power-on reset circuits
●Power
failure detection
■GENERAL
DESCRIPTION
■FEATURES
Detect Voltage Range
Hysteresis Range
: 1.6V ~ 5.0V, +2%
(100mV increments)
: V
DF
x 5%, TYP.
(XC6101~XC6107)
V
DF
x 0.1%, TYP.
(XC6111~XC6117)
: 1.0V ~ 6.0V
The XC6101~XC6107, XC6111~XC6117 series are
groups of high-precision, low current consumption voltage
detectors with manual reset input function and watchdog
functions incorporating CMOS process technology. The
series consist of a reference voltage source, delay circuit,
comparator, and output driver.
With the built-in delay circuit, the XC6101 ~ XC6107,
XC6111 ~ XC6117 series’ ICs do not require any external
components to output signals with release delay time.
Moreover, with the manual reset function, reset can be
asserted at any time. The ICs produce two types of
output; V
DFL
(low when detected) and V
DFH
(high when
detected).
With the XC6101 ~ XC6105, XC6111 ~ XC6115 series’
ICs, the WD pin can be left open if the watchdog function
is not used.
Whenever the watchdog pin is opened, the internal
counter clears before the watchdog timeout occurs.
Since the manual reset pin is internally pulled up to the V
IN
pin voltage level, the ICs can be used with the manual
reset pin left unconnected if the pin is unused.
The detect voltages are internally fixed 1.6V ~ 5.0V in
increments of 100mV, using laser trimming technology.
Six watchdog timeout period settings are available in a
range from 6.25msec to 1.6sec.
Seven release delay time 1 are available in a range from
3.13msec to 1.6sec.
Operating Voltage Range
Detect Voltage Temperature
Characteristics
: +100ppm/
O
C (TYP.)
Output Configuration
: N-channel open drain,
CMOS
Watchdog Pin
: Watchdog input
If watchdog input maintains
‘H’ or ‘L’ within the watchdog
timeout period, a reset signal
is output to the RESET
output pin
Manual Reset Pin
: When driven ‘H’ to ‘L’ level
signal, the MRB pin voltage
asserts forced reset on the
output pin.
Release Delay Time
: 1.6sec, 400msec, 200msec,
100msec, 50msec, 25msec,
3.13msec (TYP.) can be
selectable.
Watchdog Timeout Period
: 1.6sec, 400msec, 200msec,
100msec, 50msec,
6.25msec (TYP.) can be
selectable.
■TYPICAL
APPLICATION CIRCUIT
■TYPICAL
PERFORMANCE
CHARACTERISTICS
●Supply
Current vs. Input Voltage
XC61X1~XC61X5 (2.7V)
30
Supply Current:
ISS (µA)
25
20
15
10
5
0
0
1
2
3
4
5
Input Voltage:
VIN (V)
6
Ta=-40
℃
Ta=25
℃
Ta=85
℃
* Not necessary with CMOS output products.
* ‘x’ represents both ‘0’ and ‘1’. (ex. XC61x1⇒XC6101 and XC6111)
XC6101_07_XC6111_17 ETR0207_009
1/26
XC6101~XC6107, XC6111~XC6117 Series
■PIN
CONFIGURATION
●SOT-25
XC6101, XC6102 Series
XC6111, XC6112 Series
V
IN
5
WD
4
XC6103 & XC6113 Series
V
IN
5
WD
4
XC6104, XC6105 Series
XC6114, XC6115 Series
V
IN
5
WD
4
XC6106, XC6107 Series
XC6116, XC6117 Series
V
IN
5
MRB
4
1
RESETB
2
V
SS
3
MRB
1
RESET
2
V
SS
3
MRB
1
RESETB
2
3
1
RESETB
2
3
V
SS
RESET
V
SS
RESET
SOT-25 (TOP VIEW)
SOT-25 (TOP VIEW)
SOT-25 (TOP VIEW)
SOT-25 (TOP VIEW)
●USP-6C
XC6101, XC6102 Series
XC6111, XC6112 Series
XC6103 & XC6113 Series
XC6104, XC6105 Series
XC6114, XC6115 Series
XC6106, XC6107 Series
XC6116, XC6117 Series
USP-6C (BOTTOM VIEW)
USP-6C (BOTTOM VIEW)
USP-6C (BOTTOM VIEW)
USP-6C (BOTTOM VIEW)
* The dissipation pad for the USP-6C package should be
solder-plated in recommended mount pattern and metal
masking so as to enhance mounting strength and heat
release. If the pad needs to be connected to other pins, it
should be connected to the V
SS
pin.
■PIN
ASSIGNMENT
PIN NUMBER
XC6101, XC6102
XC6103
XC6104, XC6105 XC6106, XC6107
PIN NAME
XC6111, XC6112
XC6113
XC6114, XC6115 XC6116, XC6117
SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C
1
2
3
4
5
-
4
5
2
1
6
-
-
2
3
4
5
1
-
5
2
1
6
4
1
2
-
4
5
3
4
5
-
1
6
2
1
2
4
-
5
3
4
5
1
-
6
2
R
ESETB
V
SS
M
RB
WD
V
IN
RESET
FUNCTION
Reset Output
(V
DFL
: Low Level When Detected)
Ground
Manual Reset
Watchdog
Power Input
Reset Output
(V
DFH:
High Level When Detected)
2/26
XC6101 ~ XC6107, XC6111~ XC6117
Series
■PRODUCT
CLASSIFICATION
●Selection
Guide
MANUAL
RESET
Available
Available
Available
Not Available
Not Available
Available
Available
CMOS
N-channel open drain
-
CMOS
N-channel open drain
CMOS
N-channel open drain
RESET OUTPUT
V
DFL
(RESETB)
V
DFH
(RESET)
-
-
CMOS
CMOS
CMOS
CMOS
CMOS
SERIES
XC6101
XC6102
XC6103
XC6104
XC6105
XC6106
XC6107
XC6111
XC6112
XC6113
XC6114
XC6115
XC6116
XC6117
WATCHDOG
Available
Available
Available
Available
Available
Not Available
Not Available
●Ordering
Information
XC61①②③④⑤⑥⑦⑧
DESIGNATOR
①
DESCRIPTION
Hysteresis Range
Functions and
Type of Reset Output
SYMBOL
0
1
1~7
A
B
C
③
Release Delay Time *
D
E
F
H
0
1
④
Watchdog Timeout Period
2
3
4
5
6
⑤⑥
⑦
⑧
Detect Voltage
Package
Device Orientation
16 ~ 50
M
E
R
L
DESCRIPTION
: V
DF
x 5% (TYP.) with hysteresis
: V
DF
x 0.1% (TYP.) without hysteresis
: Watchdog and manual functions, and reset
output type as per Selection Guide in the above
chart
: 3.13msec (TYP.)
: 25msec (TYP.)
: 50msec (TYP.)
: 100msec (TYP.)
: 200msec (TYP.)
: 400msec (TYP.)
: 1.6sec (TYP.)
: No WD timeout period for
XC6106, XC6107, XC6116, XC6117 Series
: 6.25msec (TYP.)
: 50msec (TYP.)
: 100msec (TYP.)
: 200msec (TYP.)
: 400msec (TYP.)
: 1.6sec (TYP.)
: Detect voltage
ex.) 4.5V:
⑤⇒4, ⑥⇒5
: SOT-25
: USP-6C
: Embossed tape, standard feed
: Embossed tape, reverse feed
②
* Please set the release delay time shorter than or equal to the watchdog timeout period.
ex.) XC6101D427MR or XC6101D327MR
3/26
XC6101 ~ XC6107, XC6111~ XC6117
Series
■MARKING
RULE
●SOT-25
①
Represents product series
MARK
PRODUCT SERIES
0
XC6101xxxxxx
1
XC6102xxxxxx
2
XC6103xxxxxx
3
XC6104xxxxxx
4
XC6105xxxxxx
5
XC6106xxxxxx
6
XC6107xxxxxx
MARK
7
8
9
A
B
C
D
PRODUCT SERIES
XC6111xxxxxx
XC6112xxxxxx
XC6113xxxxxx
XC6114xxxxxx
XC6115xxxxxx
XC6116xxxxxx
XC6117xxxxxx
①
②
③ ④
SOT-25
(TOP VIEW)
②
Represents release delay time and watchdog timeout period
RELEASE
RELEASE
WATCH DOG
PRODUCT
WATCH DOG
MARK
MARK
DELAY
DELAY
TIMEOUT PERIOD
SERIES
TIMEOUT PERIOD
TIME
TIME
A
3.13msec XC61X6, XC61X7 series XC61xxA0xxxx
E
50msec
400msec
0
3.13msec
6.25msec
XC61xxA1xxxx
F
50msec
1.6sec
1
3.13msec
50msec
XC61xxA2xxxx
D
100msec XC61X6, XC61X7 series
2
3.13msec
100msec
XC61xxA3xxxx
H
100msec
100msec
3
3.13msec
200msec
XC61xxA4xxxx
K
100msec
200msec
4
3.13msec
400msec
XC61xxA5xxxx
L
100msec
400msec
5
3.13msec
1.6sec
XC61xxA6xxxx
M
100msec
1.6sec
B
25msec XC61X6, XC61X7 series XC61xxB0xxxx
E
200msec XC61X6, XC61X7 series
6
25msec
50msec
XC61xxB2xxxx
P
200msec
200msec
7
25msec
100msec
XC61xxB3xxxx
R
200msec
400msec
8
25msec
200msec
XC61xxB4xxxx
S
200msec
1.6sec
9
25msec
400msec
XC61xxB5xxxx
F
400msec XC61X6, XC61X7 series
A
25msec
1.6sec
XC61xxB6xxxx
T
400msec
400msec
C
50msec XC61X6, XC61X7 series XC61xxC0xxxx
U
400msec
1.6sec
B
50msec
50msec
XC61xxC2xxxx
H
1.6sec
XC61X6, XC61X7 series
C
50msec
100msec
XC61xxC3xxxx
V
1.6sec
1.6sec
D
50msec
200msec
XC61xxC4xxxx
PRODUCT
SERIES
XC61xxC5xxxx
XC61xxC6xxxx
XC61xxD0xxxx
XC61xxD3xxxx
XC61xxD4xxxx
XC61xxD5xxxx
XC61xxD6xxxx
XC61xxE0xxxx
XC61xxE4xxxx
XC61xxE5xxxx
XC61xxE6xxxx
XC61xxF0xxxx
XC61xxF5xxxx
XC61xxF6xxxx
XC61xxH0xxxx
XC61xxH6xxxx
③
Represents detect voltage
MARK
DETECT VOLTAGE
F
1.6
H
1.7
K
1.8
L
1.9
M
2.0
N
2.1
P
2.2
R
2.3
S
2.4
T
2.5
U
2.6
V
2.7
X
2.8
Y
2.9
Z
3.0
0
3.1
1
3.2
2
3.3
PRODUCT SERIES
XC61Xxxx16xx
XC61Xxxx17xx
XC61Xxxx18xx
XC61Xxxx19xx
XC61Xxxx20xx
XC61Xxxx21xx
XC61Xxxx22xx
XC61Xxxx23xx
XC61Xxxx24xx
XC61Xxxx25xx
XC61Xxxx26xx
XC61Xxxx27xx
XC61Xxxx28xx
XC61Xxxx29xx
XC61Xxxx30xx
XC61Xxxx31xx
XC61Xxxx32xx
XC61Xxxx33xx
MARK
3
4
5
6
7
8
9
A
B
C
D
E
F
H
K
L
M
DETECT VOLTAGE
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
PRODUCT SERIES
XC61Xxxx34xx
XC61Xxxx35xx
XC61Xxxx36xx
XC61Xxxx37xx
XC61Xxxx38xx
XC61Xxxx39xx
XC61Xxxx40xx
XC61Xxxx41xx
XC61Xxxx42xx
XC61Xxxx43xx
XC61Xxxx44xx
XC61Xxxx45xx
XC61Xxxx46xx
XC61Xxxx47xx
XC61Xxxx48xx
XC61Xxxx49xx
XC61Xxxx50xx
④
Represents production lot number
0 to 9 and A to Z and inverted 0 to 9 and A to Z repeated. (G, I, J, O, Q, W expected.)
* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)
5/26
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
