TDF8591TH
2
×
100 W SE (4
Ω)
or 1
×
310 W BTL (4
Ω)
class-D amplifier
Rev. 01 — 5 March 2008
Product data sheet
1. General description
The TDF8591TH is a high-efficiency class-D audio power amplifier with low power
dissipation for application in car audio systems. The typical output power is 2
×
100 W
into 4
Ω.
The TDF8591TH is available in an HSOP24 power package with a small internal heat
sink. Depending on the supply voltage and load conditions, a small or even no external
heat sink is required. The amplifier operates over a wide supply voltage range from
±14
V
to
±29
V and consumes a low quiescent current.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Zero dead time switching
Advanced output current protection
No DC offset induced pop noise at mode transitions
High efficiency
Supply voltage from
±14
V to
±29
V
Low quiescent current
Usable as a stereo Single-Ended (SE) amplifier or as a mono amplifier in Bridge-Tied
Load (BTL)
Fixed gain of 26 dB in SE and 32 dB in BTL
High BTL output power: 310 W into 4
Ω
Suitable for speakers in the 2
Ω
to 8
Ω
range
High supply voltage ripple rejection
Internal oscillator or synchronized to an external clock
Full short-circuit proof outputs across load and to supply lines
Thermal foldback and thermal protection
AEC-Q100 qualified
3. Ordering information
Table 1.
Ordering information
Package
Name
TDF8591TH
HSOP24
Description
plastic, heatsink small outline package; 24 leads; low stand-off height
Version
SOT566-3
Type number
NXP Semiconductors
TDF8591TH
2
×
100 W SE (4
Ω)
or 1
×
310 W BTL (4
Ω)
class-D amplifier
4. Block diagram
V
DDA2
3
V
DDA1
10
STABI DIAG
18
13
V
DDP2
23
V
DDP1
14
15
IN1M
IN1P
9
8
INPUT
STAGE
PWM
MODULATOR
RELEASE1
SWITCH1
ENABLE1
SGND1
OSC
MODE
11
7
6
OSCILLATOR
MODE
MANAGER
TEMPERATURE SENSOR
CURRENT PROTECTION
VOLTAGE PROTECTION
mute
STABI
CONTROL
AND
HANDSHAKE
DRIVER
HIGH
BOOT1
16
OUT1
DRIVER
LOW
V
SSP1
TDF8591TH
V
DDP2
22
BOOT2
SGND2
2
mute
ENABLE2
SWITCH2
INPUT
STAGE
PWM
MODULATOR
RELEASE2
CONTROL
AND
HANDSHAKE
DRIVER
HIGH
21
IN2P
IN2M
5
4
OUT2
DRIVER
LOW
17
V
SSP1
20
V
SSP2
001aah194
1
V
SSA2
12
V
SSA1
24
V
SSD
19
n.c.
Fig 1. Block diagram
5. Pinning information
5.1 Pinning
V
SSD
24
V
DDP2
23
BOOT2 22
OUT2 21
V
SSP2
20
n.c. 19
STABI 18
V
SSP1
17
OUT1 16
BOOT1 15
V
DDP1
14
DIAG 13
001aah195
1
2
3
4
5
V
SSA2
SGND2
V
DDA2
IN2M
IN2P
MODE
OSC
IN1P
IN1M
TDF8591TH
6
7
8
9
10 V
DDA1
11 SGND1
12 V
SSA1
Fig 2. Pin configuration (top view)
TDF8591TH_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 March 2008
2 of 34
NXP Semiconductors
TDF8591TH
2
×
100 W SE (4
Ω)
or 1
×
310 W BTL (4
Ω)
class-D amplifier
5.2 Pin description
Table 2.
Symbol
V
SSA2
SGND2
V
DDA2
IN2M
IN2P
MODE
OSC
IN1P
IN1M
V
DDA1
SGND1
V
SSA1
DIAG
V
DDP1
BOOT1
OUT1
V
SSP1
STABI
n.c.
V
SSP2
OUT2
BOOT2
V
DDP2
V
SSD
[1]
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Description
negative analog supply voltage for channel 2
signal ground for channel 2
positive analog supply voltage for channel 2
negative audio input for channel 2
positive audio input for channel 2
mode selection input: standby, mute or operating
oscillator frequency adjustment or tracking input
positive audio input for channel 1
negative audio input for channel 1
positive analog supply voltage for channel 1
signal ground for channel 1
negative analog supply voltage for channel 1
diagnostic for activated current protection
positive power supply voltage for channel 1
bootstrap capacitor for channel 1
PWM output from channel 1
negative power supply voltage for channel 1
decoupling of internal stabilizer for logic supply
not connected
negative power supply voltage for channel 2
PWM output from channel 2
bootstrap capacitor for channel 2
positive power supply voltage for channel 2
negative digital supply voltage
[1]
The heatsink is internally connected to V
SSD
.
6. Functional description
6.1 Introduction
The TDF8591TH is a dual channel audio power amplifier using class-D technology. The
audio input signal is converted into a Pulse Width Modulated (PWM) signal via an analog
input stage and PWM modulator. To enable the output power transistors to be driven, this
digital PWM signal is applied to a control and handshake block and driver circuits for both
the high-side and low-side. An external 2nd-order low-pass filter converts the PWM output
signal to an analog audio signal across the loudspeakers.
TDF8591TH_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 March 2008
3 of 34
NXP Semiconductors
TDF8591TH
2
×
100 W SE (4
Ω)
or 1
×
310 W BTL (4
Ω)
class-D amplifier
The TDF8591TH contains two independent amplifier channels with a differential input
stage, high output power, high efficiency (90 %), low distortion and a low quiescent
current. The amplifier channels can be connected in the following configurations:
•
Mono Bridge-Tied Load (BTL) amplifier
•
Dual Single-Ended (SE) amplifiers
The TDF8591TH also contains circuits common to both channels such as the oscillator, all
reference sources, the mode functionality and a digital timing manager. For protection a
thermal foldback, temperature, current and voltage protection are built in.
6.2 Mode selection
The TDF8591TH can be switched in three operating modes via pin MODE:
•
Standby mode; the amplifiers are switched off to achieve a very low supply current
•
Mute mode; the amplifiers are switching idle (50 % duty cycle), but the audio signal at
the output is suppressed by disabling the VI-converter input stages
•
Operating mode; the amplifiers are fully operational with output signal
The input stage (see
Figure 1)
contributes to the DC offset measured at the amplifier
output. To avoid pop noise the DC output offset voltage should be increased gradually at a
mode transition from mute to operating, or vice versa, by limiting the dV
MODE
/dt on pin
MODE, resulting in a small dV
O(offset)
/dt for the DC output offset voltage. The required time
constant for a gradually increase of the DC output offset voltage between mute and
operating is generated via an RC network on pin MODE. An example of a switching circuit
for driving pin MODE is illustrated in
Figure 3
and explained in
Table 3.
V
DDP
5.6 kΩ
5.6 kΩ
MODE
5.6 kΩ
5.6 V
S1
S2
100
µF
(10 V)
SGND
001aad836
Fig 3. Example of mode selection circuit
Table 3.
S1
closed
closed
open
open
Mode selection
S2
closed
open
closed
open
Mode selection
Standby mode
Standby mode
Mute mode
Operating mode
TDF8591TH_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 March 2008
4 of 34
NXP Semiconductors
TDF8591TH
2
×
100 W SE (4
Ω)
or 1
×
310 W BTL (4
Ω)
class-D amplifier
The value of the RC time constant should be dimensioned for 500 ms. If the 100
µF
capacitor is left out of the application the voltage on pin MODE will be applied with a much
smaller time constant, which might result in audible pop noises during start-up (depending
on DC output offset voltage and used loudspeaker).
In order to fully charge the coupling capacitors at the inputs, the amplifier will remain
automatically in Mute mode for approximately 150 ms before switching to Operating
mode. A complete overview of the start-up timing is given in
Figure 4.
audio
switching
V
MODE
operating
5V
2.5 V
mute
0 V (SGND)
standby
100 ms
>50
ms
time
audio
switching
V
MODE
operating
5V
0 V (SGND)
standby
100 ms
50 ms
time
001aad837
Fig 4. Timing on mode selection input
6.3 Pulse width modulation frequency
The output signal of the amplifier is a PWM signal with a switching frequency that is set by
an external resistor R
ext(OSC)
connected between pins OSC and V
SSA
. An optimum setting
for the carrier frequency is between 300 kHz and 350 kHz. An external resistor R
ext(OSC)
of
30 kΩ sets the frequency to 310 kHz.
TDF8591TH_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 5 March 2008
5 of 34
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