TDA9950
CEC/I
2
C-bus translator
Rev. 02 — 22 October 2009
Product data sheet
1. General description
The TDA9950 is a single-chip CEC/I
2
C-bus translator with a processor, dedicated to the
control and interfacing of the Consumer Electronics Control (CEC), a feature of the
High-Definition Multimedia Interface (HDMI).
The TDA9950 is an interface between the CEC protocol and timings and the standard
I
2
C-bus. A message received on the I
2
C-bus interface is written in a buffer and sent on the
CEC line. A message received from the CEC line is stored in a buffer, and an interrupt is
generated indicating that a message can be read via the I
2
C-bus. To reduce its power
consumption the TDA9950 sets itself to Idle mode when there is no message on the CEC
line nor on the I
2
C-bus.
2. Features
2.1 Principal features
I
I
I
I
I
I
I
I
Receive and transmit CEC messages with compliant Signal Free Time handling
I
2
C-bus interface to host supporting 100 kbit/s and 400 kbit/s communication
Supports multiple CEC logical addresses
Supports CEC messages up to 16 bytes in length
Programmable retry count
Comprehensive arbitration and collision handling
3.0 V to 3.6 V V
DD
operating range
Automatic Idle mode to reduce power consumption when there is no message on CEC
line and I
2
C-bus
I
I/O pins are 5 V tolerant
2.2 Additional features
I
Processor with embedded software to control the interface between CEC line and
I
2
C-bus
I
Active-LOW reset input and on-chip power-on reset allows operation without external
reset components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets.
I
On-chip oscillator for 12 MHz crystal
I
Schmitt trigger port inputs
NXP Semiconductors
TDA9950
CEC/I
2
C-bus translator
3. Applications
I
I
I
I
I
I
I
All devices using an HDMI connector
YC
B
C
R
or RGB high-speed video digitizer
Projector, plasma and LCD TV
Rear-projection TV
High-end TV
Home-theater amplifier
DVD recorder
4. Quick reference data
Table 1.
Symbol
V
DD
T
amb
P
tot
Quick reference data
Parameter
supply voltage
ambient temperature
total power dissipation
Operating mode
Idle mode
I
2
C-bus: (5 V tolerant) pins SDA and SCL
f
clk
clock frequency
Standard mode
Fast mode
-
-
-
-
100
400
kHz
kHz
Conditions
Min
3.0
0
-
-
Typ
3.3
-
33
16
Max
3.6
70
46.8
25.2
Unit
V
°C
mW
mW
5. Ordering information
Table 2.
Ordering information
Package
Name
TDA9950TT
TSSOP20
Description
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT360-1
Type number
TDA9950_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2009
2 of 22
NXP Semiconductors
TDA9950
CEC/I
2
C-bus translator
6. Block diagram
TDA9950
CEC_IN
CEC-BUS
CEC_OUT
internal
bus
DATA RAM
CPU
A0
A1
SCL
SDA
I
2
C-BUS
INTERRUPT
INT
INT_POL
XTAL1
CRYSTAL
XTAL2
CONFIGURABLE
OSCILLATOR
POWER-ON RESET
RST
001aag922
Fig 1.
Block diagram
7. Pinning information
7.1 Pinning
RSVD1
INT
CEC_OUT
RST
V
SS
XTAL1
XTAL2
CEC_IN
SDA
1
2
3
4
5
6
7
8
9
20 A0
19 A1
18 INT_POL
17 RSVD7
16 RSVD6
15 V
DD
14 RSVD5
13 RSVD4
12 RSVD3
11 RSVD2
001aag923
TDA9950
SCL 10
Fig 2.
Pin configuration
7.2 Pin description
Table 3.
Symbol
RSVD1
INT
Pin description
Pin
1
2
Type
[1]
I
O
Description
RSVD1 —
Reserved pin; shall be connected to ground
INT —
Interrupt line to the host processor to indicate data is
available for reading. The polarity of this signal depends on the
state of pin INT_POL.
CEC_OUT —
Output for CEC line (open-drain).
CEC_OUT
3
O
TDA9950_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2009
3 of 22
NXP Semiconductors
TDA9950
CEC/I
2
C-bus translator
Pin description
…continued
Pin
4
5
6
7
8
9
10
11
12
13
14
15
Type
[1]
I
P
I
O
I
I/O
I
I
O
O
I
P
Description
RST —
External reset input. A LOW state on this pin resets the
translator.
Ground:
0 V reference (GND).
XTAL1 —
Input to the oscillator circuit and internal clock
generator circuits (12 MHz crystal).
XTAL2 —
Output from the oscillator amplifier.
CEC_IN —
Input for CEC line.
SDA —
I
2
C-bus serial data input/output (open-drain).
SCL —
I
2
C-bus serial clock input.
RSVD2 —
Reserved pin (should be connected to ground).
RSVD3 —
Reserved pin.
RSVD4 —
Reserved pin.
RSVD5 —
Reserved pin (should be connected to ground).
Power supply —
This is the (core digital 3.3 V) power supply
voltage for normal operation as well as Idle and Power-down
modes.
RSVD6 —
Reserved pin (should be connected to ground).
RSVD7 —
Reserved pin (should be connected to ground).
INT_POL —
Sets the polarity of the active output required on
the INT signal (pin 2). Leave floating or pull-up to V
DD
for a
HIGH output when active (rising edge), connect to V
SS
for a
LOW output when active (falling edge). This input is latched at
reset.
A1 —
I
2
C-bus slave address bit 2.
A0 —
I
2
C-bus slave address bit 1.
Table 3.
Symbol
RST
V
SS
XTAL1
XTAL2
CEC_IN
SDA
SCL
RSVD2
RSVD3
RSVD4
RSVD5
V
DD
RSVD6
RSVD7
INT_POL
16
17
18
I
I
I
A1
A0
[1]
19
20
I
I
I = input, O = output, P = power supply.
8. Functional description
The TDA9950 uses an internal processor with embedded software to control the interface
between the CEC line and the I
2
C-bus.
8.1 Device addressing
The TDA9950 is a slave I
2
C-bus device and the SCL pin is an input pin only. The timing
and protocol for the I
2
C-bus are standard.
Table 4.
Bit
Value
[1]
Device address code
Device code
b7
[1]
0
b6
1
b5
1
b4
0
b3
1
Chip enable
b2
A1
b1
A0
R/W
b0
R/W
Address code
The Most Significant Bit (MSB), b7, is sent first.
A1 and A0 are hardware-selectable pins.
TDA9950_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2009
4 of 22
NXP Semiconductors
TDA9950
CEC/I
2
C-bus translator
In case of independent CEC, a system could have up to four TDA9950 devices on the
same I
2
C-bus.
The four addresses are defined by the state of the inputs A0 and A1 (logic 1 when
connected to V
DD
, logic 0 when connected to GND).
8.2 Configuring the TDA9950
The TDA9950 is controlled via a series of registers.
Table 5.
Register
APR
CSR
CER
CVR
CCR
ACKH
ACKL
CCONR
CDR
I
2
C-bus register configuration
Description
Address Pointer Register
TDA9950 Status Register
TDA9950 Error Register
TDA9950 Version Register
TDA9950 Control Register
CEC Address ACK High register
CEC Address ACK Low register
CEC Configuration Register
CEC Data Registers
Address
00h
00h
01h
02h
03h
04h
05h
06h
07h - 19h
Read/Write
W
R
R
R
R/W
R/W
R/W
R/W
R/W
The first byte of any I
2
C-bus write frame configures the address pointer register APR,
which determines the first TDA9950 register that will be read or written in the remainder of
the I
2
C-bus transfer. If a read is carried out without a prior write to the address pointer
register, the register returned will be that to which the address pointer register was last
set.
The address pointer auto-increments after a successful read or write for all address
pointer values other than 00h. Auto-incremented addresses above 19h are invalid and
ignored.
Registers 01h to 06h are used for configuration of the TDA9950, whilst repeated
auto-incremented reads starting at register 07h are used to transfer CEC data. Setting the
address pointer register higher than 07h is treated as setting it to 07h, as all message
data transfers must start from register 07h and continue by auto-incrementing in one
contiguous transfer. Transfers via the data registers are formatted using the data register
protocol described in
Section 8.5.
8.3 Use of the INT line
As the TDA9950 is an I
2
C-bus slave device, it provides an additional I/O line to signal to
the host that data is available for reading. This is the INT output line, which should be
monitored by the host. An additional TDA9950 input, on pin INT_POL, allows
configuration of the polarity of operation of the INT line. When the INT line is active, it will
match the state of the input on pin INT_POL.
The state of the INT line is always reflected in the TDA9950 Status Register, so it is
possible to regularly poll this register instead of monitoring the INT line. However, this
method is less efficient and not recommended. The INT indication in the TDA9950 Status
Register is not affected by the setting of the INT polarity input on pin INT_POL.
TDA9950_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2009
5 of 22
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