VSC8115-05 and VSC8115-06
P
RODUCT
B
RIEF
155 Mbps and 622 Mbps Clock and Data Recovery Units
Vitesse’s high-speed clock and data recovery devices deliver industry-leading jitter performance
Vitesse’s newly improved multirate clock and data recovery (CDR) devices
provide exceptional input sensitivity, jitter tolerance, and jitter transfer
performance.
The VSC8115-05 and VSC8115-06 devices derive high-speed timing
signals for SONET/SDH-based equipment. The devices are designed to
operate with SONET framer or ASIC devices to provide a low-power,
high-speed clock and data recovery interface for optical networks.
The devices achieve impressive jitter tolerance of 0.45 UI, jitter input
sensitivity of 150 mV, and jitter transfer compliance in JMODE. Meets all
Telcordia, ANSI, ITU-T, and SONET jitter requirements.
The VSC8115-05 and VSC8115-06 feature signal and lock-detect status
outputs, automatic lock-to-reference, and PLL bypass for on-board
debugging. High-speed outputs are configurable for either LVPECL or
LVDS.
Available in a 20-pin TSSOP package for flexible implementation and
simplified layout, the VSC8115-05 device supports commercial temperature
ranges, and the VSC8115-06 supports industrial temperature ranges. Both
devices come in tape and reel form and are available in lead(Pb)-free
versions.
Highlights
• Superior jitter tolerance and
transfer jitter performance
• Low power dissipation
• Single CDR unit for both 155 Mbps
and 622 Mbps applications
Applications
• SONET/SDH and DWDM
transport systems
• Multiservice access platforms and
add/drop multiplexers
• ATM switches and routers
• Digital cross-connect systems
• Optical test equipment
VSC8115-05
VSC8115-06
STS12
Divider
CAP
VCO
BYPASS
DATAIN ±
SD
LOCKREFN
0
REFCLK
1
2
CLKOUT ±
2
Phase/
Frequency
Detector
Loop Filter
2
DATAOUT ±
LOCKDET
Use the VSC8115-05 or VSC8115-06 for OC-12 (STM-4) and OC-3 (STM-1) NRZ data clocking and recovery.
www.vitesse.com
VSC8115-05 and VSC8115-06
Features
• Automatic lock-to-reference
• Signal and lock-detect status outputs
• PLL bypass for on-board debugging
• High-speed LVPECL or LVDS outputs
Key Specifications
• 3.3 V power supply
• 155 mW typical power dissipation
• Commercial temperature range 0 °C to 85 °C
• Industrial temperature range –40 °C to 95 °C
• 20-pin, 4.4 mm × 6.5 mm TSSOP package
Requirements
• Telcordia, ANSI, ITU-T G.783, and G.825 SDH
• GR-253 CORE and GR-253 ILR SONET
• T1.105.03-2002 SONET
Related Vitesse Products
Visit
www.vitesse.com
for information about these related
Vitesse products:
• VSC8115 Multirate Clock and Data Recovery Unit
OC-3 Jitter Tolerance Minimum Specifications
100
Input Jitter Amplitude (UIpp)
10
1
VSC8115-05 and VSC8115-06
Typical Performance
0.1
Telec ordia Requirements
0.01
1
10
100
1K
10K
100K
1M
10M
Jitter Frequency (Hz)
OC-12 Jitter Tolerance Minimum Specifications
100
10
Jitter (UIp-p)
1
VSC8115-05 and VSC8115-06
Typical Performance
0.1
Telec ordia Requirements
0.01
1
10
100
1K
10K
100K
1M
10M
Jitter Frequency (Hz)
© 2008 by Vitesse Semiconductor Corporation. VPPD-02210 Revision 1.0. Vitesse Semiconductor Corporation ("Vitesse") retains the right to make changes to its products or spec-
ifications. As such, all information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without
notice at any time, and Vitesse assumes no responsibility for use of any information herein. Nothing contained herein conveys to the purchaser of microelectronic devices any
license under the patent or any other intellectual property rights of any manufacturer. Vitesse®, and numerous other trademarks, are trademarks of Vitesse in the United States
and/or other jurisdictions. Other trademarks used herein that are not the property of Vitesse are the property of their respective owners.
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