TDA9981B
HDMI transmitter up to 150 MHz pixel rate with 3
×
8-bit video
inputs and 4
×
I
2
S-bus with S/PDIF
Rev. 01 — 4 July 2008
Product data sheet
1. General description
The TDA9981B is an HDMI transmitter (which also supports DVI) that enables a 3
×
8-bit
RGB or YCbCr video stream (with a pixel rate up to 150 MHz for the TDA9981BHL/15
version), up to 4 I
2
S-bus audio streams (with an audio sampling rate up to 192 kHz) and
the additional information required by all the HDMI 1.2a standards.
In order to be compatible with most applications, the TDA9981B integrates a full
programmable input formatter and color space conversion block. The video input formats
accepted are YCbCr 4 : 4 : 4 (up to 3
×
8-bit), YCbCr 4 : 2 : 2 semi-planar (up to
2
×
12-bit), YCbCr 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1
×
12-bit).
For ITU656-like formats, double edges are supported so that data can be sampled on
rising and falling edges.
The device can be controlled via an I
2
C-bus interface.
2. Features
I
3
×
8-bit video data input bus, CMOS and LV-TTL compatible
I
Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs or
VREF, HREF and FREF could be used for input data synchronization
I
Pixel rate clock input can be made active on one or both edges (selectable by I
2
C-bus)
I
The TDA9981B has 4 I
2
S-bus audio input channels and 1 S/PDIF channel; audio
sampling rate up to 192 kHz
I
250 MHz to 1.50 GHz HDMI transmitter operation
I
Programmable input formatter and upsampler/interpolator allows input of any of the
4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656 and ITU656-like formats
I
Programmable color space converter:
N
RGB to YCbCr
N
YCbCr to RGB
I
Controllable via I
2
C-bus
I
Low power dissipation
I
1.8 V and 3.3 V power supplies
I
Power-down mode
I
Hard reset
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
3. Applications
I
I
I
I
I
I
I
I
I
DVD players and recorders
Set-Top Box (STB)
AV receivers and amplifiers (repeater)
Camcorders
Digital still cameras
Media players
PVRs
Media centers PCs, graphics add-in boards, notebook PCs
Switches
4. Quick reference data
Table 1.
Quick reference data
V
DDA(FRO_3V3)
= 3.0 V to 3.6 V; V
DDA(PLL_3V3)
= 3.0 V to 3.6 V; V
DDH(3V3)
= 3.0 V to 3.6 V;
V
DDD(3V3)
= 3.0 V to 3.6 V; V
DDC(1V8)
= 1.65 V to 1.95 V; V
PP
= 0 V; T
amb
= 0
°
C to 85
°
C.
Typical values are measured at V
DDA(FRO_3V3)
= V
DDA(PLL_3V3)
= V
DDH(3V3)
= V
DDD(3V3)
= 3.3 V;
V
DDC(1V8)
= 1.8 V; V
PP
= 0 V and T
amb
= 25
°
C; unless otherwise specified.
Symbol
V
DDA(FRO_3V3)
V
DDA(PLL_3V3)
V
DDD(3V3)
V
DDH(3V3)
V
DDC(1V8)
T
amb
f
clk(max)
P
cons
P
tot
P
pd
Parameter
free running oscillator 3.3 V
analog supply voltage
PLL 3.3 V analog supply
voltage
digital supply voltage (3.3 V)
HDMI supply voltage (3.3 V)
core supply voltage (1.8 V)
ambient temperature
maximum clock frequency
power consumption
total power dissipation
power dissipation in
Power-down mode
maximum clock frequency
power consumption
total power dissipation
power dissipation in
Power-down mode
[2]
[2]
[2]
[1]
[1]
[1]
Conditions
Min
3.0
3.0
3.0
3.0
1.65
0
81
-
-
-
Typ
3.3
3.3
3.3
3.3
1.8
-
-
235
369
14
Max
3.6
3.6
3.6
3.6
1.95
85
-
288
438
19
Unit
V
V
V
V
V
°C
MHz
mW
mW
mW
TDA9981BHL/8 and TDA9981BHL/15
TDA9981BHL/8; up to 81 MHz
TDA9981BHL/15; up to 150 MHz
f
clk(max)
P
cons
P
tot
P
pd
[1]
[2]
150
-
-
-
-
-
MHz
mW
mW
mW
381.5 468
515.5 618
14
19
Worst case: video input format: 720p at 60 Hz (RGB 4 : 4 : 4 embedded sync), video output format:
720p at 60 Hz (YCbCr 4 : 4 : 4).
Video input format: 1080p (RGB 4 : 4 : 4 embedded sync, rising edge), video output format:
1080p (RGB 4 : 4 : 4).
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
2 of 41
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
5. Ordering information
Table 2.
Ordering information
Package
Name
TDA9981BHL
LQFP80
Description
plastic low profile quad flat package; 80 leads;
body 12
×
12
×
1.4 mm
Version
SOT315-1
Type number
5.1 Ordering options
Table 3.
Survey of type numbers
Sampling frequency
(MHz)
81
150
Application
customer specific version
customer specific version
Extended type number
TDA9981BHL/8/C1xx
TDA9981BHL/15/C1xx
TDA9981B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 4 July 2008
3 of 41
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Product data sheet
Rev. 01 — 4 July 2008
© NXP B.V. 2008. All rights reserved.
TDA9981B_1
6. Block diagram
NXP Semiconductors
V
PP
RST_N
42
3
V
DDC(1V8)
V
DDD(3V3)
V
DDH(3V3)
V
DDA(PLL_3V3)
28, 34
38
I2C_SCL
43
I2C_SDA
44
A0
41
A1
40
20
DDC_SCL
DDC_SDA
V
DDA(FRO_3V3)
13, 48, 16, 45, 23
71
59, 74
HPD
18
HPD
MANAGEMENT
HARD
RESET
I
2
C-BUS
SLAVE
DDC-BUS
19
AP7 to AP0
ACLK
4 to 11
12
AUDIO
PROCESSING
YCbCr
DATA
ISLAND
PACKET
IRQ
GENERATION
17
INT
INFORMATION
FRAMES AND
PACKETS
68 to 70,
75 to 79
57 and 58,
61 to 65,
67
49 to 56
2
1
80
66
VIDEO
INPUT
PROCESSOR
27
26
30
VIDEO PROCESSING
RGB
YCbCr 4 : 4 : 4
3
×
8-bit
UPSAMPLING
FROM
4:2:2
TO
4 : 4 : 4
(1)
COLOR
SPACE
CONVERTER
RGB TO YUV
YUV TO RGB
(4 : 4 : 4)
(1)
DOWNSAMPLING
FROM
4:4:4
TO
4 : 2 : 2
(1)
HDMI
SERIALIZER
29
33
32
36
35
TXC+
TXC−
TX0+
TX0−
TX1+
TX1−
TX2+
TX2−
VPA[7:0]
VPB[7:0]
VPC[7:0]
VSYNC/VREF
HSYNC/HREF
DE/FREF
VCLK
YCbCr 4 : 2 : 2
ITU656 or ITU656-like
14, 47,
72
V
SSD
2
×
12-bit
or 1
×
12-bit
15, 60,
73
V
SSC
25, 31,
37
V
SSH
TDA9981B
150 MHz pixel rate HDMI transmitter
22
V
SSA(FRO_3V3)
39
V
SSA(PLL_3V3)
46
V
SSA(PLL_1V8)
21
TM
24
EXT_SWING
001aai221
TDA9981B
(1) Block can be bypassed.
4 of 41
Fig 1.
Block diagram
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
7. Pinning information
7.1 Pinning
71 V
DDD(3V3)
80 DE/FREF
74 V
DD(1V8)
69 VPA[6]
68 VPA[7]
65 VPB[1]
79 VPA[0]
78 VPA[1]
77 VPA[2]
76 VPA[3]
75 VPA[4]
70 VPA[5]
67 VPB[0]
64 VPB[2]
63 VPB[3]
62 VPB[4]
HSYNC/HREF
VSYNC/VREF
V
PP
AP7
AP6
AP5
AP4
AP3
AP2
1
2
3
4
5
6
7
8
9
61 VPB[5]
66 VCLK
73 V
SSC
72 V
SSD
60 V
SSC
59 V
DDC(1V8)
58 VPB[6]
57 VPB[7]
56 VPC[0]
55 VPC[1]
54 VPC[2]
53 VPC[3]
52 VPC[4]
51 VPC[5]
50 VPC[6]
49 VPC[7]
48 V
DDD(3V3)
47 V
SSD
46 V
SSA(PLL_1V8)
45 V
DDC(1V8)
44 I2C_SDA
43 I2C_SCL
42 RST_N
41 A0
AP1 10
AP0 11
ACLK 12
V
DDD(3V3)
13
V
SSD
14
V
SSC
15
V
DDC(1V8)
16
INT 17
HPD 18
DDC_SDA 19
DDC_SCL 20
TDA9981B
TM 21
V
SSA(FRO_3V3)
22
V
DDA(FRO_3V3)
23
EXT_SWING 24
V
SSH
25
TXC− 26
TXC+ 27
V
DDH(3V3)
28
TX0− 29
TX0+ 30
V
SSH
31
TX1− 32
TX1+ 33
V
DDH(3V3)
34
TX2− 35
TX2+ 36
V
SSH
37
V
DDA(PLL_3V3)
38
V
SSA(PLL_3V3)
39
A1 40
001aai219
Fig 2.
Pin configuration
7.2 Pin description
Table 4.
Symbol
Pin description
Pin Type
[1]
Description
I
I
P
I
I
I
horizontal synchronization or reference input
vertical synchronization or reference input
programming voltage if OTP memory is available (must always be
connected to the ground of the digital core in normal operation)
audio port 7 input; auxiliary (AUX)
audio port 6 input; S/PDIF stream
audio port 5 input; optional master clock MCLK for S/PDIF
© NXP B.V. 2008. All rights reserved.
HSYNC/HREF 1
VSYNC/VREF 2
V
PP
AP7
AP6
AP5
TDA9981B_1
3
4
5
6
Product data sheet
Rev. 01 — 4 July 2008
5 of 41
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