PN511
Transmission Module
Rev. 3.3 — 13 June 2007
082733
Product short data sheet
1. Introduction
This Product short data sheet describes the functionality of the transceiver IC PN511. It
includes functional and electrical specifications. A complete specification is given in the
product data sheet.
2. General description
The PN511 is a highly integrated transceiver IC for contactless communication at
13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation
concept completely integrated for different kinds of contactless communication methods
and protocols at 13.56 MHz.
The PN511 transceiver ICs support 3 different operating modes
•
Reader/Writer mode supporting ISO 14443A/Mifare and FeliCa scheme
•
Card Operation mode supporting ISO 14443A/Mifare and FeliCa scheme
•
NFCIP-1 mode
Enabled in Reader/Writer mode for ISO 14443A/Mifare, the PN511’s internal transmitter
part is able to drive a reader/writer antenna designed to communicate with ISO 14443A/
Mifare cards and transponders without additional active circuitry. The receiver part
provides a robust and efficient implementation of a demodulation and decoding circuitry
for signals from ISO 14443A/Mifare compatible cards and transponders. The digital part
handles the complete ISO 14443A framing and error detection (Parity & CRC).
The PN511 supports Mifare Classic (e.g. Mifare Standard) products. The PN511 supports
contactless communication using Mifare higher transfer speeds up to 424 kbit/s in both
directions.
Enabled in Reader/Writer mode for FeliCa, the PN511 transceiver IC supports the FeliCa
communication scheme. The receiver part provides a robust and efficient implementation
of the demodulation and decoding circuitry for FeliCa coded signals. The digital part
handles the FeliCa framing and error detection like CRC. The PN511 supports contactless
communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
In Card Operation mode, the PN511 transceiver IC is able to answer to a reader/writer
command either according to the FeliCa or ISO 14443A/Mifare card interface scheme.
The PN511 generates the digital load modulated signals and in addition with an external
circuit the answer can be sent back to the reader/writer. A complete card functionality is
only possible in combination with a secure core IC using the S
2
C interface.
NXP Semiconductors
PN511
Transmission Module
Additionally, the PN511 transceiver IC offers the possibility to communicate directly to an
NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication
mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092
NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error
detection.
Various host controller interfaces are implemented:
•
•
•
•
8-bit parallel interface
1
SPI interface
serial UART (similar to RS232 with voltage levels according pad voltage supply)
I
2
C interface.
1.
082733
8-bit parallel Interface only available in HVQFN40 package.
© NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 — 13 June 2007
2 of 22
NXP Semiconductors
PN511
Transmission Module
3. Features
Highly integrated analog circuitry to demodulate and decode responses
Buffered output drivers to connect an antenna with minimum number of external
components
Integrated RF Level detector
Integrated data mode detector
ISO 14443A/Mifare support
Typical operating distance in Reader/Writer mode for communication to a ISO 14443A/
Mifare or FeliCa card up to 50 mm depending on the antenna size, tuning and power
supply
Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna
size and tuning and power supply
Typical operating distance in ISO 14443A/Mifare card or FeliCa Card Operation mode
of about 100 mm depending on the antenna size and tuning and the external field
strength
Mifare Classic encryption in Reader/Writer mode support
ISO 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s
Contactless communication according to the FeliCa scheme at 212 kbit/s and
424 kbit/s
Integrated RF interface for NFCIP-1 up to 424 kbit/s
S
2
C interface
Supported host controller interfaces
SPI interface up to 10 Mbit/s
I
2
C interface up to 400 kbit/s in Fast mode, up to 3400 kbit/s in High-speed mode
serial UART in different transfer speeds up to 1228.8 kbit/s, framing according to
the RS232 interface with voltage levels according pad voltage supply
8-bit parallel interface with and without Address Latch Enable
Comfortable 64 byte send and receive FIFO-buffer
Flexible interrupt modes
Hard reset with low power function
Power-down mode per software
Programmable timer
Internal oscillator to connect 27.12 MHz quartz
2.5-3.6 V power supply
CRC Co-processor
Free programmable I/O pins
Internal self test
082733
© NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 — 13 June 2007
3 of 22
NXP Semiconductors
PN511
Transmission Module
4. Quick reference data
Table 1.
Symbol
AV
DD
DV
DD
TV
DD
PV
DD
I
HPD
Hard Power-down Current
AV
DD
= DV
DD
=
TV
DD
= PV
DD
= 3 V,
N
RESET
= LOW
AV
DD
= DV
DD
= TV
DD
= PV
DD
=
3 V, RF level detector on
DV
DD
= 3 V
AV
DD
= 3 V, bit RCVOff = 0
AV
DD
= 3 V, bit RCVOff = 1
[5]
Quick reference data
Parameter
Supply Voltage
Conditions
AV
SS
= DV
SS
= PV
SS
= TV
SS
= 0 V,
PV
DD
≤
AV
DD
= DV
DD
=TV
DD
[1][2]
[1][2]
[1][2]
[3]
[7]
Min
2.5
Typ
-
Max
3.6
Unit
V
1.6
-
-
-
3.6
5
V
μA
I
SPD
I
DVDD
I
AVDD
I
AVDD,RCVOFF
I
PVDD
I
TVDD
T
amb
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Soft Power-down Current
Digital Supply Current
Analog Supply Current
Analog Supply Current,
receiver switched off
Pad Supply Current
Transmitter Supply Current
operating ambient temperature
[7]
-
-
-
-
-
-
-30
-
6.5
7
3
-
60
10
9
10
5
40
100
+85
μA
mA
mA
mA
mA
mA
°C
Continuous Wave
[4][6][8]
Supply voltage below 3 V reduces the performance (e.g. the achievable operating distance).
AV
DD
, DV
DD
and TV
DD
shall always be on the same voltage level.
PV
DD
shall always be on the same or lower voltage level than DV
DD
.
I
TVDD
depends on TV
DD
and the external circuitry connected to Tx1 and Tx2
I
PVDD
depends on the overall load at the digital pins.
During operation with a typical circuitry the overall current is below 100 mA.
I
SPD
and I
HPD
are the total currents over all supplies.
Typical value using a complementary driver configuration and an antenna matched to 40
Ω
between TX1 and TX2 at 13.56 MHz
5. Ordering information
Table 2.
Ordering information
Package
Name
PN5110A0HN1/C2
PN5110A0HN/C2
HVQFN32
HVQFN40
Description
Plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5
×
5
×
0.85 mm
Plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6× 6× 0.85 mm
Version
SOT617
SOT618
Type number
082733
© NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 — 13 June 2007
4 of 22
NXP Semiconductors
PN511
Transmission Module
6. Block diagram
The Analog interface handles the modulation and demodulation of the analog signals
according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode
communication scheme.
The RF level detector detects the presence of an external RF-field delivered by the
antenna to the RX pin.
The Data mode detector detects a Mifare, FeliCa or NFCIP-1 mode in order to prepare the
internal receiver to demodulate signals, which are sent to the PN511.
The communication (S
2
C) interface provides digital signals to support communication for
transfer speeds above 424 kbit/s and digital signals to communicate to a secure smart
card IC.
082733
© NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 — 13 June 2007
5 of 22
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