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74LVT16501A
3.3 V LVT 18-bit universal bus transceiver; 3-state
Rev. 04 — 19 May 2006
Product data sheet
1. General description
The 74LVT16501A is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock (CPAB and CPBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.
When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level.
If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH
transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the
outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
18-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA to
−32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Positive-edge triggered clock inputs
Latch-up protection:
N
JESD78: exceeds 500 mA
I
ESD protection:
N
MIL STD 883, method 3015: exceeds 2000 V
N
Machine model: exceeds 200 V
Philips Semiconductors
74LVT16501A
3.3 V LVT 18-bit universal bus transceiver; 3-state
3. Quick reference data
Table 1.
Quick reference data
GND = 0 V; T
amb
= 25
°
C.
Symbol Parameter
t
PLH
t
PHL
C
i
C
io
I
CC
propagation delay An to Bn or
Bn to An
propagation delay An to Bn or
Bn to An
input capacitance (control pins)
input/output capacitance
(I/O pins)
quiescent supply current
Conditions
C
L
= 50 pF;
V
CC
= 3.3 V
C
L
= 50 pF;
V
CC
= 3.3 V
V
I
= 0 V or 3.0 V
outputs disabled;
V
I/O
= 0 V or 3.0 V
outputs disabled;
V
CC
= 3.6 V
Min
-
-
-
-
-
Typ
1.9
1.9
3
9
70
Max
-
-
-
-
-
Unit
ns
ns
pF
pF
µA
4. Ordering information
Table 2.
Ordering information
Package
Temperature range Name
74LVT16501ADL
−40 °C
to +85
°C
SSOP56
TSSOP56
Description
plastic shrink small outline package; 56 leads;
body width 7.5 mm
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
Version
SOT371-1
SOT364-1
Type number
74LVT16501ADGG
−40 °C
to +85
°C
74LVT16501A_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 19 May 2006
2 of 19
Philips Semiconductors
74LVT16501A
3.3 V LVT 18-bit universal bus transceiver; 3-state
5. Functional diagram
1
OEAB
55
CPAB
2
LEAB
30 28 27 55 2
LEBA
OEBA
LEAB
CPBA
CPAB
1
OEAB
27
OEBA
30
CPBA
28
LEBA
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D
4
1
1
1
6D
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
001aad339
001aad338
Fig 1. Logic symbol
Fig 2. IEC logic symbol
OEAB
CPAB
LEAB
LEBA
CPBA
OEBA
A0
1
55
2
28
30
27
3
ID
C1
CLK
ID
C1
CLK
54
B0
to 17 other channels
001aaf011
Fig 3. Logic diagram
74LVT16501A_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 19 May 2006
3 of 19
Philips Semiconductors
74LVT16501A
3.3 V LVT 18-bit universal bus transceiver; 3-state
6. Pinning information
6.1 Pinning
OEAB
LEAB
A0
GND
A1
A2
V
CC
A3
A4
1
2
3
4
5
6
7
8
9
56 GND
55 CPAB
54 B0
53 GND
52 B1
51 B2
50 V
CC
49 B3
48 B4
47 B5
46 GND
45 B6
44 B7
43 B8
42 B9
41 B10
40 B11
39 GND
38 B12
37 B13
36 B14
35 V
CC
34 B15
33 B16
32 GND
31 B17
30 CPBA
29 GND
001aaf010
A5 10
GND 11
A6 12
A7 13
A8 14
A9 15
A10 16
A11 17
GND 18
A12 19
A13 20
A14 21
V
CC
22
A15 23
A16 24
GND 25
A17 26
OEBA 27
LEBA 28
74LVT16501A
Fig 4. Pin configuration
6.2 Pin description
Table 3.
Symbol
OEAB
LEAB
A0
GND
A1
A2
V
CC
A3
74LVT16501A_4
Pin description
Pin
1
2
3
4
5
6
7
8
Description
A-to-B output enable input
A-to-B latch enable input
data input or output A0
ground (0 V)
data input or output A1
data input or output A2
voltage supply
data input or output A3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 19 May 2006
4 of 19
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