Si53340-45 Data Sheet
Low-Jitter LVDS Fanout Clock Buffers with up to 10 LVDS Out-
puts from Any-Format Input and Wide Frequency Range from dc
up to 1250 MHz
The Si53340-45 family of LVDS fanout buffers is ideal for clock/data distribution and re-
dundant clocking applications. These devices feature typical ultra-low jitter of 50 fs and
operate over a wide frequency range from dc to 1250 MHz. Built-in LDOs deliver high
PSRR performance and reduces the need for external components simplifying low jitter
clock distribution in noisy environments.
They are available in multiple configurations and offer a selectable input clock using a
2:1 input mux. Other features include independent output enable and built-in format
translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to
deliver end-to-end clock tree performance.
KEY FEATURES
• Ultra-low additive jitter: 50 fs rms
• Built-in LDOs for high PSRR performance
• Up to 10 LVDS Outputs
• Any-format Inputs (LVPECL, Low-Power
LVPECL, LVDS, CML, HCSL, LVCMOS)
• Wide frequency range: dc to 1250 MHz
• Output Enable option
• Multiple configuration options
• 2:1 Input Mux
• RoHS compliant, Pb-free
• Temperature range: –40 to +85 °C
VDD
Power Supply
Filtering
4
4 Outputs
Si53340/41
VDDOA
OEAb
CLK0*
0
3
3
3 Outputs
Si53342/43
CLK1*
CLK_SEL
1
3 Outputs
OEBb
VDDOB
10
10 Outputs
Si53344/45
*Si53341/43/45 require Single-ended Inputs
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Rev. 1.2
Si53340-45 Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si5334x Ordering Guide
Part Number
SI53340-B-GM
SI53341-B-GM
SI53342-B-GM
SI53343-B-GM
SI53344-B-GM
SI53345-B-GM
Input
2:1 selectable MUX
Any-format
2:1 selectable MUX
LVCMOS
2:1 selectable MUX
Any-format
2:1 selectable MUX
LVCMOS
2:1 selectable MUX
Any-format
2:1 selectable MUX
LVCMOS
LVDS Output
1 bank / 4 Outputs
1 bank / 4 Outputs
2 banks / 3 Outputs
2 banks / 3 Outputs
1 bank / 10 Outputs
1 bank / 10 Outputs
Output Enable (OE)
—
—
1 per bank
1 per bank
—
—
Frequency Range
dc to 1250 MHz
dc to 200 MHz
dc to 1250 MHz
dc to 200 MHz
dc to 1250 MHz
dc to 200 MHz
Package
16-QFN
3 x 3 mm
16-QFN
3 x 3 mm
24-QFN
4 x 4 mm
24-QFN
4 x 4 mm
32-QFN
5 x 5 mm
32-QFN
5 x 5 mm
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Si53340-45 Data Sheet
Functional Description
2. Functional Description
The Si53340-45 are a family of low-jitter, low skew, fixed format (LVDS) buffers. The Si53340/42/44 have a universal input that accepts
most common differential or LVCMOS input signals, while the Si53341/43/45 accept only LVCMOS inputs. These devices are available
in multiple configurations customized for the end application (refer to
1. Ordering Guide
for more details on configurations).
2.1 Universal, Any-Format Input Termination (Si53340/42/44)
The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, Low-power LVPECL, LVDS,
CML, HCSL, and LVCMOS. The tables below summarize the various ac- and dc-coupling options supported by the device. For the best
high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks, the fastest
possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance. Though not re-
quired, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766:
Understanding and Optimizing Clock Buffer’s Additive Jitter Performance”
for more information.
Table 2.1. Clock Input Options
Clock Format
AC-Coupled
LVPECL/Low-power LVPECL
LVCMOS
LVDS
HCSL
CML
DC-Coupled
LVPECL/Low-power LVPECL
LVCMOS
LVDS
HCSL
CML
N/A
No
No
No
No
Yes
Yes
Yes
Yes (3.3 V)
No
N/A
No
Yes
No
Yes
Yes
Yes
Yes
Yes (3.3 V)
Yes
1.8 V
2.5/3.3 V
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Si53340-45 Data Sheet
Functional Description
V
DD
0.1 µF
CLKx
100
CLKxb
Si53340/42/44
0.1 µF
Figure 2.1. Differential (HCSL, LVPECL, Low-Power LVPECL, LVDS, CML) AC-Coupled Input Termination
V
DD
DC-Coupled
V
DD
= 3.3 V or 2.5 V
CMOS
Driver
50
Rs
1k
V
DD
Si53340/42/44
CLKx
CLKxb
V
TERM
= V
DD
/2
1k
V
DD
V
DD
AC-Coupled
V
DD
= 3.3 V or 2.5 V
CMOS
Driver
1k
1k
V
DD
Si53340/42/44
CLKx
V
BIAS
= V
DD
/2
50
Rs
1k
CLKxb
Note:
Value for Rs should be chosen so that the total
source impedance matches the characteristic
impedance of the PCB trace.
1k
V
TERM
= V
DD
/2
Figure 2.2. Single-Ended (LVCMOS) Input Termination
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Si53340-45 Data Sheet
Functional Description
V
DD
DC Coupled LVPECL Input Termination Scheme 1
R
1
V
DD
= 3.3 V or 2.5 V
“Standard”
LVPECL
Driver
50
50
R
2
3.3 V LVPECL:
R
1
= 127 Ohm, R
2
= 82.5 Ohm
2.5 V LVPECL:
R
1
= 250 Ohm, R
2
= 62.5 Ohm
R
2
CLKx
CLKxb
R
1
V
DD
Si53340/42/44
V
TERM
= V
DD
– 2V
R
1
// R
2
= 50 Ohm
DC Coupled LVPECL Input Termination Scheme 2
V
DD
= 3.3 V or 2.5 V
“Standard”
LVPECL
Driver
50
50
50
50
CLKx
CLKxb
V
DD
Si53340/42/44
V
TERM
= V
DD
– 2 V
DC Coupled LVDS Input Termination
V
DD
= 3.3 V or 2.5 V
Standard
LVDS
Driver
50
100
50
CLKx
CLKxb
V
DD
Si53340/42/44
DC Coupled HCSL Input Termination Scheme
V
DD
= 3.3 V
Standard
HCSL Driver
33
50
33
50
50
50
CLKx
CLKxb
V
DD
Si53340/42/44
Note: 33 Ohm series termination is optional depending on the location of the receiver.
Figure 2.3. Differential DC-Coupled Input Terminations
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