3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Features
◆
◆
◆
IDT71V016
Description
The IDT71V016 is a 1,048,576-bit high-speed Static RAM
organized as 64K x 16. It is fabricated using IDT’s high-perfomance,
high-reliability CMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost-effective solution for high-speed memory needs.
The IDT71V016 has an output enable pin which operates as fast
as 7ns, with address access times as fast as 12ns. All bidirectional
inputs and outputs of the IDT71V016 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous circuitry
is used, requiring no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin
Plastic SOJ and 44-pin TSOP Type II.
◆
◆
◆
◆
◆
◆
64K x 16 advanced high-speed CMOS Static RAM
Commercial (0° to +70°C) and Industrial (–40°C to +85°C)
Equal access and cycle times
— Commercial and Industrial: 15/20ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V (±0.3V) power supply
Available in 44-pin Plastic SOJ and 44-pin TSOP
package.
Functional Block Diagram
OE
Output
Enable
Buffer
A
0
- A
15
Address
Buffers
CS
Chip
Enable
Buffer
WE
O
Write
Enable
Buffer
Byte
Enable
Buffers
N N
I
A
T CE
6S NS
R S
01 IG
A E
V S
P L
71 DE
O
ER W
S
D E
B
R N
Row / Column
Decoders
I/O
15
8
High
Byte
I/O
Buffer
8
I/O
8
C
E
O R
O
F
64K x 16
Memory
Array
16
Sense
Amps
and
Write
Drivers
I/O
7
8
Low
Byte
I/O
Buffer
8
I/O
0
BHE
BLE
3211 drw 01
AUGUST 2000
1
©2000 Integrated Device Technology, Inc.
DSC-3211/08
IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configuration
A
4
A
3
A
2
A
1
A
0
CS
I/O
0
I/O
1
I/O
2
I/O
3
V
DD
Vss
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
Vss
V
DD
Pin Description
SO44-1
SO44-2
SOJ/TSOP
Top View
Truth Table
(1)
CS
H
L
L
L
L
L
L
L
L
OE
X
L
L
L
X
X
X
H
X
O
WE
X
H
H
H
L
L
L
H
X
N N
I
A
T CE
6S NS
R S
01 IG
A E
V S
P L
71 DE
O
ER W
S
D E
B
R N
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
3211 drw 02
C
E
BLE
X
L
H
L
L
L
H
X
H
O R
O
F
BHE
X
H
L
L
L
H
L
X
H
I/O
0
-I/O
7
High-Z
I/O
8
-I/O
15
High-Z
High-Z
DATA
OUT
DATA
OUT
DATA
IN
High-Z
DATA
IN
High-Z
High-Z
Function
Deselected – Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
3211 tbl 02
DATA
OUT
High-Z
DATA
OUT
DATA
IN
DATA
IN
High-Z
High-Z
High-Z
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
6.42
2
IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
T
A
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–0.5 to +4.6
–0.5 to V
CC
+0.5
0 to +70
–55 to +125
–55 to +125
1.0
50
Unit
V
V
o
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
GND
0V
0V
V
DD
3.3V ± 0.3V
3.3V ± 0.3V
3211 tbl 04
C
C
C
o
o
Recommended DC Operating
Conditions
Symbol
V
DD
Parameter
Supply Voltage
Supply Voltage
Input High Voltage – Inputs
Input High Voltage – I/O
Input Low Voltage
Min.
Typ.
3.3
0
—
____
____
Max.
3.6
0
4.6
V
DD
+0.3
0.8
Unit
V
V
V
V
V
3211 tbl 05
W
mA
3211 tbl 03
GND
V
IH
V
IH
V
IL
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. Input, Output,and I/O terminals; 4.6V maximum.
DC Electrical Characteristics
(V
DD
= 3.3V ± 0.3V, Commercial and Industrial Temperature Ranges)
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
DC Electrical Characteristics
(V
DD
= 3.3V ± 0.3V, V
LC
= 0.2V, V
HC
= V
DD
–0.2V)
Symbol
I
CC
Parameter
O
N N
I
A
T CE
6S NS
R S
01 IG
A E
V S
P L
71 DE
O
ER W
S
D E
B
R N
2.0
–0.5
(1)
NOTE:
1. V
IL
(min.) = –1.5V for pulse width less than tRC/2, once per cycle.
C
E
3.0
0
2.0
Capacitance
Symbol
C
IN
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
Max.
6
7
Unit
pF
pF
C
I/O
V
OUT
= 3dV
3211 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
IDT71V016
Test Condition
Min.
___
___
___
Max.
5
5
Unit
µA
µA
V
V
3211 tbl 07
V
DD
= Max., V
IN
= GND to V
DD
V
DD
= Max.,
CS
= V
IH
, V
OUT
= GND to V
DD
O R
O
F
(1)
I
OL
= 8mA, V
DD
= Min.
0.4
___
I
OH
= –4mA, V
DD
= Min.
2.4
71V016S15
Com'l
130
Ind.
130
71V016S20
Com'l.
120
Ind.
120
Unit
mA
Dynam ic Operating Current
CS
≤
V
IL
, Outputs Open, V
DD
= Max., f = f
MAX
(2)
Standby Power Supply Current (TTL Level)
CS
≥
V
IH
, Outputs Open, V
DD
= Max., f = f
MAX
(2)
Standby Power Supply Current (CMOS Level)
CS
≥
V
HC
, Outputs Open, V
DD
= Max., f = 0
(2)
V
IN
≤
V
LC
or V
IN
≥
V
HC
I
SB
35
35
30
30
mA
I
SB1
5
7
5
7
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing .
3211 tbl 08
6.42
3
IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3211 tbl 09
AC Test Loads
3.3V
DATA
OUT
30pF*
Figure 1. AC Test Load
∆t
AA,
t
ACS
(Typical, ns) 5
4
3
2
1
•
O
N N
I
A
T CE
6S NS
R S
01 IG
A E
V S
P L
71 DE
O
ER W
S
D E
B
R N
3.3V
320Ω
C
E
320Ω
DATA
OUT
350Ω
5pF*
350Ω
3211 drw 04
3211 drw 05
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
7
6
O R
O
F
•
•
•
•
•
•
8 20 40 60 80 100 120 140 160 180 200
CAPACITANCE (pF)
Figure 3. Output Capacitive Derating
3211 drw 06
6.42
4
IDT71V016, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
Symbol
READ CYCLE
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
BE
t
BLZ
(1)
t
BHZ
(1)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Parameter
(V
DD
= 3.3V ± 0.3V, Commercial and Industrial Temperature Ranges)
71V016S15
Min.
Max.
Min.
71V016S20
Max.
Unit
15
____
____
____
20
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
____
20
20
____
5
____
5
____
6
8
____
____
____
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
WRITE CYCLE
t
WC
t
AW
t
CW
t
BW
t
AS
t
WR
t
WP
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
Address Hold from End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
O
N N
I
A
T CE
6S NS
R S
01 IG
A E
V S
P L
71 DE
O
ER W
S
D E
B
R N
____
0
6
4
—
8
—
0
C
0
5
0
____
E
8
10
____
8
—
____
10
____
____
____
6
____
8
15
10
____
____
____
____
____
____
____
____
____
20
____
____
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3211 tbl 10
12
12
12
0
0
10
10
0
0
10
8
12
10
0
0
Timing Waveform of Read Cycle No. 1
(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
3211 drw 07
O R
O
F
1
____
1
____
____
6
____
8
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3.
OE, BHE,
and
BLE
are LOW.
6.42
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
