ispLSI 1048EA
®
In-System Programmable High Density PLD
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Eight Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally Compatible with ispLSI 1048C and 1048E
• NEW FEATURES
— 100% IEEE 1149.1 Boundary Scan Testable
— ispJTAG™ In-System Programmable Via IEEE 1149.1
(JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O supports Mixed
Voltage Systems (V
CCIO
Pin)
— Open Drain Output Option
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 170 MHz Maximum Operating Frequency
—
t
pd
= 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
A0
Output Routing Pool
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
D7
D5
Output Routing Pool
D Q
A1
A2
A3
A4
A5
A6
A7
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
D6
Logic
D Q
Global Routing Pool (GRP)
Array
D Q
GLB
D4
D3
D2
D1
D0
D Q
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
CLK
0139A/1048EA
Description
The ispLSI 1048EA is a High Density Programmable
Logic Device containing 288 Registers, 96 Universal I/O
pins, eight Dedicated Input pins, four Dedicated Clock
Input pins, two dedicated Global OE input pins, and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 1048EA features 5V in-system programmability
and in-system diagnostic capabilities via IEEE 1149.1
Test Access Port. The ispLSI 1048EA offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect to provide truly reconfigurable systems. A functional
superset of the ispLSI 1048 architecture, the ispLSI
1048EA device adds user selectable 3.3V or 5V I/O and
open-drain output options.
The basic unit of logic on the ispLSI 1048EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinato-
rial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
1048ea_03
1
Specifications
ispLSI 1048EA
Functional Block Diagram
Figure 1. ispLSI 1048EA Functional Block Diagram
I/O I/O I/O I/O
95 94 93 92
RESET
GOE 0
GOE 1
I/O I/O I/O I/O
91 90 89 88
I/O I/O I/O I/O
87 86 85 84
I/O I/O I/O I/O
83 82 81 80
IN IN
11 10
I/O I/O I/O I/O
79 78 77 76
I/O I/O I/O I/O
75 74 73 72
I/O I/O I/O I/O
71 70 69 68
I/O I/O I/O I/O
67 66 65 64
IN
9
IN
8
Input Bus
Generic
Logic Blocks
(GLBs)
F7
F6
Output Routing Pool (ORP)
F5
F4
F3
F2
F1
F0
E7
E6
Input Bus
Output Routing Pool (ORP)
E5
E4
E3
E2
E1
E0
IN 7
IN 6
I/O 63
I/O 62
I/O 61
I/O 60
VCCIO
D7
I/O 0
I/O 1
I/O 2
I/O 3
A0
A1
D6
Output Routing Pool (ORP)
D5
I/O 59
I/O 58
I/O 57
Output Routing Pool (ORP)
D4
D3
D2
D1
D0
lnput Bus
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
Global
Routing
Pool
(GRP)
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
C0
C1
C2
C3
C4
C5
C6
C7
Clock
Distribution
Network
Megablock
TDI
TDO
TMS
TCK
IN 2
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
IN
4
I/O I/O I/O I/O
32 33 34 35
I/O I/O I/O I/O
36 37 38 39
I/O I/O I/O I/O
40 41 42 43
I/O I/O I/O I/O
44 45 46 47
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
Input Bus
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Y Y Y Y
0 1 2 3
0139F/1048EA
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered
input, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source
2mA or sink 8mA. Each output can be programmed
independently for fast or slow output slew rate to
minimize overall output switching noise. By connecting
the VCCIO pin to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat-
ible voltages.
Eight GLBs, 16 I/O cells, dedicated inputs (if available)
and one ORP are connected together to make a
Megablock (Figure 1). The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1048EA device contains six Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1048EA device are selected using
the Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0). The logic
of this GLB allows the user to create an internal clock
from a combination of internal signals within the device.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 1048EA are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
2
Specifications
ispLSI 1048EA
Boundary Scan
Figure 2. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
T
btsu
T
btch
TCK
T
btcl
T
bth
T
btcp
T
btvo
TDO
Valid Data
T
btco
Valid Data
T
btoz
T
btcpsu
Data to be
captured
T
btcph
Data Captured
T
btuov
Data to be
driven out
T
btuco
Valid Data
T
btuoz
Valid Data
Symbol
t
btcp
t
btch
tbtcl
tbtsu
tbth
trf
tbtco
tbtoz
tbtvo
tbtcpsu
tbtcph
tbtuco
tbtuoz
tbtuov
Parameter
TCK [BSCAN test] clock pulse width
TCK [BSCAN test] pulse width high
TCK [BSCAN test] pulse width low
TCK [BSCAN test] setup time
TCK [BSCAN test] hold time
TCK [BSCAN test] rise and fall time
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to data output disable
TAP controller falling edge of clock to data output enable
BSCAN test Capture register setup time
BSCAN test Capture register hold time
BSCAN test Update reg, falling edge of clock to valid output
BSCAN test Update reg, falling edge of clock to output disable
BSCAN test Update reg, falling edge of clock to output enable
Min
100
50
50
20
25
50
–
–
–
40
25
–
–
–
Max
–
–
–
–
–
–
25
25
25
–
–
50
50
50
Units
ns
ns
ns
ns
ns
mV/ns
ns
ns
ns
ns
ns
ns
ns
ns
3
Specifications
ispLSI 1048EA
Absolute Maximum Ratings
1
Supply Voltage V
cc
. ................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Supply Voltage
Supply Voltage: Output Drivers
Input Low Voltage
Input High Voltage
Commercial
5V
3.3V
T
A
= 0°C to + 70°C
MIN.
4.75
4.75
3.0
0
2.0
MAX.
5.25
5.25
3.6
0.8
V
cc
+1
UNITS
V
V
V
V
V
V
CC
V
CCIO
V
IL
V
IH
Table 2-0005/1048EA
Capacitance (T
A
=25
o
C, f=1.0 MHz)
SYMBOL
PARAMETER
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
Y0 Clock Capacitance
TYPICAL
8
10
UNITS
pf
pf
TEST CONDITIONS
V
CC
= 5.0V, V
PIN
= 2.0V
V
CC
= 5.0V, V
PIN
= 2.0V
Table 2-0006/1048EA
C
1
C
2
Erase/Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
MINIMUM
10000
MAXIMUM
–
UNITS
Cycles
Table 2-0008/1048EA
4
Specifications
ispLSI 1048EA
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 3
Table 2-0003/1048EA
Figure 3. Test Load
+ 5V
R1
Device
Output
R2
CL
*
Test
Point
Output Load Conditions (see Figure 3)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
470Ω
∞
470Ω
∞
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
Table 2-0004a
*
CL includes Test Fixture and Probe Capacitance.
0213a
C
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I
OL
= 8 mA
I
OH
= -2 mA, V
CCIO
= 3.0V
I
OH
= -4 mA, V
CCIO
= 4.75V
0V
≤
V
IN
≤
V
IL
(Max.)
(V
CCIO
- 0.2)V
≤
V
IN
≤
V
CCIO
V
CCIO
≤
V
IN
≤
5.25V
0V
≤
V
IN
≤
V
IL
V
CCIO
= 5.0V or 3.3V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 3.0V
f
TOGGLE
= 1 MHz
CONDITION
MIN.
—
2.4
2.4
—
—
—
—
—
—
TYP.
3
—
—
—
—
—
—
—
—
190
MAX. UNITS
0.4
—
—
-10
10
10
-200
-240
—
V
V
V
µA
µA
µA
µA
mA
mA
V
OL
V
OH
I
IL
I
IH
I
IL-PU
I
OS
1
I
CC
2, 4, 5
Table 2-0007/1048EA
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Meaured using eight 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25°C.
4. Unused inputs held at 0.0V.
5. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book CD-ROM to estimate maximum I
CC
.
5
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