Specifications
ispLSI and pLSI 1032
ispLSI and pLSI 1032
®
®
High-Density Programmable Logic
Features
•
HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 90 MHz Maximum Operating Frequency
—
f
max
= 60 MHz for Industrial and Military/883 Devices
—
t
pd
= 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E
2
CMOS Technology
— 100% Tested
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispLSI AND pLSI DEVELOPMENT TOOLS
pDS
®
Software
— Easy to Use PC Windows™ Interface
— Boolean Logic Compiler
— Manual Partitioning
— Automatic Place and Route
— Static Timing Table
ispDS+™ Software
— Industry Standard, Third Party Design
Environments
— Schematic Capture, State Machine, HDL
— Automatic Partitioning and Place and Route
— Comprehensive Logic and Timing Simulation
— PC and Workstation Platforms
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0
C7
Output Routing Pool
A2
A3
A4
Logic
Array
D Q
C5
D Q
GLB
C4
C3
D Q
A5
A6
A7
C2
C1
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
C0
CLK
Output Routing Pool
Description
The ispLSI and pLSI 1032 are High-Density Program-
mable Logic Devices containing 192 Registers, 64
Universal I/O pins, eight Dedicated Input pins, four Dedi-
cated Clock Input pins and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between
all of these elements. The ispLSI 1032 features 5-Volt in-
system programming and in-system diagnostic
capabilities. It is the first device which offers non-volatile
"on-the-fly" reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems. It is
architecturally and parametrically compatible to the pLSI
1032 device, but multiplexes four of the dedicated input
pins to control in-system programming.
The basic unit of logic on the ispLSI and pLSI 1032
devices is the Generic Logic Block (GLB). The GLBs are
labeled A0, A1 .. D7 (see figure 1). There are a total of
32 GLBs in the ispLSI and pLSI 1032 devices. Each GLB
has 18 inputs, a programmable AND/OR/XOR array, and
four outputs which can be configured to be either combi-
natorial or registered. Inputs to the GLB come from the
GRP and dedicated inputs. All of the GLB outputs are
brought back into the GRP so that they can be connected
to the inputs of any other GLB on the device.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
February 1997
1996 ISP Encyclopedia
1996 ISP Encyclopedia
1032_02
1
Output Routing Pool
A1
D Q
C6
Specifications
ispLSI and pLSI 1032
Functional Block Diagram
Figure 1. ispLSI and pLSI 1032 Functional Block Diagram
I/O I/O I/O I/O
63 62 61 60
RESET
I/O I/O I/O I/O
59 58 57 56
I/O I/O I/O I/O
55 54 53 52
I/O I/O I/O I/O
51 50 49 48
IN IN
7 6
Input Bus
Generic
Logic Blocks
(GLBs)
D7
D6
Output Routing Pool (ORP)
D5
D4
D3
D2
D1
D0
IN 5
IN 4
I/O 47
I/O 46
I/O 45
I/O 44
C7
I/O 0
I/O 1
I/O 2
I/O 3
A0
A1
Output Routing Pool (ORP)
C6
Output Routing Pool (ORP)
C5
C4
C3
C2
C1
C0
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
Input Bus
A3
A4
A5
A6
A7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
*SDI/IN 0
*MODE/IN 1
Global
Routing
Pool
(GRP)
B0
B1
B2
B3
B4
B5
B6
B7
Clock
Distribution
Network
Megablock
Output Routing Pool (ORP)
Input Bus
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
*ispEN/NC
*SDO/IN 2
*SCLK/IN 3
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
Y Y Y Y
0 1 2 3
0139(1)-32-isp
*ISP Control Functions for ispLSI 1032 Only
The devices also have 64 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
I/O pin with 3-state control. Additionally, all outputs are
polarity selectable, active high or active low. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. The I/O cells
within the Megablock also share a common Output
Enable (OE) signal. The ispLSI and pLSI 1032 devices
contain four of these Megablocks.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI and pLSI 1032 devices are selected
using the Clock Distribution Network. Four dedicated
clock pins (Y0, Y1, Y2 and Y3) are brought into the
distribution network, and five clock outputs (CLK 0, CLK
1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route
clocks to the GLBs and I/O cells. The Clock Distribution
Network can also be driven from a special clock GLB (C0
on the ispLSI and pLSI 1032 devices). The logic of this
GLB allows the user to create an internal clock from a
combination of internal signals within the device.
2
lnput Bus
I/O 4
I/O 5
I/O 6
I/O 7
A2
1996 ISP Encyclopedia
Specifications
ispLSI and pLSI 1032
Absolute Maximum Ratings
1
Supply Voltage V
cc
...................................-0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Commercial
T
A
= 0°C to +70°C
T
A
= -40°C to +85°C
T
C
= -55°C to +125°C
MIN.
4.75
4.5
4.5
0
2.0
MAX.
5.25
5.5
5.5
0.8
Vcc
+ 1
V
V
Table 2- 0005Aisp w/mil.eps
UNITS
V
CC
V
IL
V
IH
Supply Voltage
Industrial
Military/883
V
Input Low Voltage
Input High Voltage
Capacitance (T
A
=25
o
C, f=1.0 MHz)
SYMBOL
PARAMETER
Dedicated Input Capacitance
I/O and Clock Capacitance
Commercial/Industrial
Military
MAXIMUM
1
8
10
10
UNITS
pf
pf
pf
TEST CONDITIONS
V
CC
=5.0V, V
IN
=2.0V
V
CC
=5.0V, V
IN
=2.0V
V
CC
=5.0V, V
I/O
, V
Y
=2.0V
Table 2- 0006
C
1
C
2
1
.
Guaranteed but not 100% tested.
Data Retention Specifications
PARAMETER
Data Retention
ispLSI Erase/Reprogram Cycles
pLSI Erase/Reprogram Cycles
MINIMUM
20
10000
100
MAXIMUM
–
–
–
UNITS
Years
Cycles
Cycles
Table 2- 0008B
3
1996 ISP Encyclopedia
Specifications
ispLSI and pLSI 1032
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
≤
3ns 10% to 90%
1.5V
1.5V
See figure 2
Figure 2. Test Load
+ 5V
R1
Device
Output
R2
CL
*
Test
Point
3-state levels are measured 0.5V from steady-state
active level.
Table 2- 0003
Output Load Conditions (see figure 2)
*
CL includes Test Fixture and Probe Capacitance.
Test Condition
A
B
Active High
Active Low
C
Active High to Z
at
V
OH
- 0.5V
Active Low to Z
at
V
OL
+ 0.5V
R1
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
∞
470Ω
∞
470Ω
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
I
OL
=8 mA
I
OH
=-4 mA
CONDITION
MIN.
–
2.4
–
–
–
–
–
–
–
Industrial/Military
TYP.
3
–
–
–
–
–
–
–
130
135
MAX.
0.4
–
-10
10
-150
-150
-200
190
220
UNITS
V
V
µA
µA
µA
µA
mA
mA
mA
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2,4
1.
2.
3.
4.
Input or I/O Low Leakage Current 0V
≤
V
IN
≤
V
IL
(MAX.)
Input or I/O High Leakage Current 3.5V
≤
V
IN
≤
V
CC
isp Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
0V
≤
V
IN
≤
V
IL
(MAX.)
0V
≤
V
IN
≤
V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.5V, V
IH
= 3.0V Commercial
f
TOGGLE
= 1 MHz
One output at a time for a maximum duration of one second.
Measured using eight 16-bit counters.
Typical values are at V
CC
= 5V and T
A
= 25
o
C.
Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
Table 2- 0007A-32-isp
tion of this datasheet and Thermal Management section of this Data Book to estimate maximum I
CC
.
4
1996 ISP Encyclopedia
Specifications
ispLSI and pLSI 1032
External Timing Parameters
Over Recommended Operating Conditions
5 2
PARAMETER
TEST
#
COND.
DESCRIPTION
1
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
(
tsu2
1
tco1
)
+
Clock Frequency, Max
Toggle
4
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg. Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
–
–
-90
12
17
–
–
–
–
8
–
–
–
–
–
–
-80
15
20
–
–
–
–
–
–
–
–
–
–
-60
20
25
–
–
–
–
13
–
–
16
–
22.5
–
24
24
–
–
–
–
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN. MAX. MIN. MAX. MIN. MAX.
1
2
3
4
5
6
7
8
9
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
en
t
dis
t
wh
t
wl
t
su5
t
h5
1.
2.
3.
4.
5.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
–
–
–
–
S
S
10
12
17
18
18
–
–
–
–
90.9
58.8
125
6
–
0
9
–
0
–
–
–
4
4
2
6.5
80
50
7
–
0
–
0
–
–
–
5
5
2
6.5
100
60
38
83
9
–
0
13
–
0
–
13
–
–
6
6
2.5
8.5
USE 1032E-80
FOR NEW DESIG
N
10
15
15
15
–
–
–
–
10
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Ext. Sync. Clock Pulse Duration, High
17 Ext. Sync. Clock Pulse Duration, Low
18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-Bit counter using GRP feedback.
fmax
(Toggle) may be less than 1/(twh +
twl).
This is to allow for a clock duty cycle of other than 50%.
Reference Switching Test Conditions section.
USE 1032E-70
FOR NEW DESIG
N
10
10
Table 2-0030-32/90,80,60C
5
1996 ISP Encyclopedia
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