MX25U8033E
MX25U8033E
1.8V, 8M-BIT [x 1/x 2/x 4]
CMOS MXSMIO
®
(SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• HOLD feature
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Auto Erase and Auto Program Algorithm
• Low Power Consumption
• Individual Protect
P/N: PM1718
1
Rev. 1.8, October 24, 2017
MX25U8033E
Contents
1. FEATURES ............................................................................................................................................................. 5
2. GENERAL DESCRIPTION ..................................................................................................................................... 7
Table 1. Additional Feature Comparison .................................................................................................... 7
3. PIN CONFIGURATIONS ........................................................................................................................................ 8
4. PIN DESCRIPTION ................................................................................................................................................. 8
5. BLOCK DIAGRAM.................................................................................................................................................. 9
6. DATA PROTECTION............................................................................................................................................. 10
Table 2. Protected Area Sizes ...................................................................................................................11
Table 3. 4K-bit Secured OTP Definition
....................................................................................................11
7. MEMORY ORGANIZATION .................................................................................................................................. 12
Table 4. Memory Organization ................................................................................................................. 12
8. DEVICE OPERATION ........................................................................................................................................... 13
Figure 1. Serial Modes Supported ........................................................................................................... 13
9. HOLD FEATURE................................................................................................................................................... 14
Figure 2. Hold Condition Operation ........................................................................................................ 14
10. COMMAND DESCRIPTION ................................................................................................................................ 15
Table 5. Command Set ............................................................................................................................ 15
10-1.
10-2.
10-3.
10-4.
Write Enable (WREN) .............................................................................................................................. 17
Write Disable (WRDI)............................................................................................................................... 17
Read Identification (RDID)
....................................................................................................................... 17
Read Status Register (RDSR) ................................................................................................................. 17
Figure 3. Program/Erase Flow with Read Array Data .............................................................................. 18
Figure 4. Program/ Erase Flow without Read Array Data (read P_FAIL/E_FAIL flag)
............................. 19
Figure 5. WRSR Flow .............................................................................................................................. 20
Table 6. Status Register ........................................................................................................................... 21
10-5. Write Status Register (WRSR)................................................................................................................. 22
Table 7. Protection Modes ....................................................................................................................... 22
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
10-17.
10-18.
Read Data Bytes (READ) ........................................................................................................................ 23
Read Data Bytes at Higher Speed (FAST_READ) .................................................................................. 23
Dual Read Mode (DREAD) ...................................................................................................................... 23
2 x I/O Read Mode (2READ) ................................................................................................................... 24
4 x I/O Read Mode (4READ) ................................................................................................................... 24
Performance Enhance Mode ................................................................................................................... 25
Sector Erase (SE) .................................................................................................................................... 25
Block Erase (BE32K) ............................................................................................................................... 26
Block Erase (BE) ..................................................................................................................................... 26
Chip Erase (CE) ....................................................................................................................................... 26
Page Program (PP) ................................................................................................................................. 27
4 x I/O Page Program (4PP) .................................................................................................................... 27
Deep Power-down (DP) ........................................................................................................................... 27
P/N: PM1718
2
Rev. 1.8, October 24, 2017
MX25U8033E
10-19. Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 28
10-20. Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) ......................................... 28
Table 8. ID Definitions
............................................................................................................................. 29
10-21. Enter Secured OTP (ENSO) .................................................................................................................... 29
10-22. Exit Secured OTP (EXSO) ....................................................................................................................... 29
10-23. Read Security Register (RDSCUR) ......................................................................................................... 29
Table 9. Security Register Definition
........................................................................................................ 30
10-24. Write Security Register (WRSCUR)......................................................................................................... 30
10-25. Write Protection Selection (WPSEL)........................................................................................................ 30
Figure 6. WPSEL Flow............................................................................................................................ 31
10-26. Single Block Lock/Unlock Protection (SBLK/SBULK) .............................................................................. 32
Figure 7. Block Lock Flow ........................................................................................................................ 32
Figure 8. Block Unlock Flow .................................................................................................................... 33
10-27. Read Block Lock Status (RDBLOCK) ...................................................................................................... 34
10-28. Gang Block Lock/Unlock (GBLK/GBULK) ............................................................................................... 34
10-29. Read SFDP Mode (RDSFDP).................................................................................................................. 35
Figure 9. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence .......................................... 35
Table 10. Signature and Parameter Identification Data Values
............................................................... 36
Table 11. Parameter Table (0): JEDEC Flash Parameter Tables ............................................................. 37
Table 12. Parameter Table (1): Macronix Flash Parameter Tables .......................................................... 39
11. POWER-ON STATE ............................................................................................................................................ 41
12. ELECTRICAL SPECIFICATIONS ....................................................................................................................... 42
12-1. Absolute Maximum Ratings ..................................................................................................................... 42
Figure 10. Maximum Negative Overshoot Waveform .............................................................................. 42
12-2. Capacitance TA = 25°C, f = 1.0 MHz .................................................................................................... 42
Figure 11. Maximum Positive Overshoot Waveform ................................................................................ 42
Figure 12. Input Test Waveforms and Measurement Level ..................................................................... 43
Figure 13. Output Loading ....................................................................................................................... 43
Figure 14. SCLK TIMING DEFINITION ................................................................................................... 43
Table 13. DC Characteristics ................................................................................................................... 44
Table 14. AC Characteristics .................................................................................................................... 45
13. Timing Analysis ................................................................................................................................................. 46
Figure 15. Serial Input Timing .................................................................................................................. 46
Figure 16. Output Timing ......................................................................................................................... 46
Figure 17. Hold Timing ............................................................................................................................. 47
Figure 18. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 ...................................... 47
Figure 19. Write Enable (WREN) Sequence (Command 06)................................................................... 47
Figure 20. Write Disable (WRDI) Sequence (Command 04) ................................................................... 48
Figure 21. Read Identification (RDID) Sequence (Command 9F)
.......................................................... 48
Figure 22. Read Status Register (RDSR) Sequence (Command 05) ..................................................... 48
Figure 23. Write Status Register (WRSR) Sequence (Command 01) .................................................... 49
Figure 24. Read Data Bytes (READ) Sequence (Command 03) (50MHz) ............................................. 49
P/N: PM1718
Rev. 1.8, October 24, 2017
3
MX25U8033E
Figure 25. Read at Higher Speed (FAST_READ) Sequence (Command 0B) ....................................... 50
Figure 26. Dual Read Mode Sequence (Command 3B) .......................................................................... 50
Figure 27. 2 x I/O Read Mode Sequence (Command BB) ...................................................................... 51
Figure 28. 4 x I/O Read Mode Sequence (Command EB) .................................................................... 51
Figure 29. 2 x I/O Read Enhance Performance Mode Sequence (Command BB) .................................. 52
Figure 30. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) .................................. 53
Figure 31. Page Program (PP) Sequence (Command 02) .................................................................... 54
Figure 32. 4 x I/O Page Program (4PP) Sequence (Command 38) ....................................................... 54
Figure 33. Sector Erase (SE) Sequence (Command 20) ....................................................................... 55
Figure 34. Block Erase 32KB (BE32K) Sequence (Command 52) ......................................................... 55
Figure 35. Block Erase (BE) Sequence (Command D8) ........................................................................ 55
Figure 36. Chip Erase (CE) Sequence (Command 60 or C7) ................................................................ 55
Figure 37. Deep Power-down (DP) Sequence (Command B9) .............................................................. 56
Figure 38. Release from Deep Power-down and Read Electronic Signature (RES) (Command AB) .... 56
Figure 39. Release from Deep Power-down (RDP) Sequence (Command AB) ..................................... 57
Figure 40. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90/EF/DF) ........ 57
Figure 41. Read Security Register (RDSCUR) Sequence (Command 2B) ............................................. 58
Figure 42. Write Security Register (WRSCUR) Sequence (Command 2F) ............................................. 58
Figure 43. Power-up Timing ..................................................................................................................... 59
Table 15. Power-Up Timing ...................................................................................................................... 59
13-1. Initial Delivery State ................................................................................................................................. 59
14. OPERATING CONDITIONS ................................................................................................................................ 60
Figure 44. AC Timing at Device Power-Up .............................................................................................. 60
Figure 45. Power-Down Sequence .......................................................................................................... 61
15. ERASE AND PROGRAMMING PERFORMANCE ............................................................................................. 62
16. LATCH-UP CHARACTERISTICS ....................................................................................................................... 62
17. ORDERING INFORMATION ............................................................................................................................... 63
18. PART NAME DESCRIPTION .............................................................................................................................. 64
19. PACKAGE INFORMATION ................................................................................................................................. 65
19-1. 8-pin SOP (150mil) .................................................................................................................................. 65
19-2. 8-pin SOP (200mil) .................................................................................................................................. 66
19-3. 8-land WSON (6x5mm)............................................................................................................................ 67
19-4. 8-land USON (4x4mm) ............................................................................................................................ 68
19-5. 8-WLCSP (Height: 0.45mm) .................................................................................................................... 69
19-6. 8-WLCSP (Height: 0.33mm) .................................................................................................................... 70
20. REVISION HISTORY .......................................................................................................................................... 71
P/N: PM1718
4
Rev. 1.8, October 24, 2017
MX25U8033E
8M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO
(SERIAL MULTI I/O) FLASH MEMORY
1. FEATURES
GENERAL
• Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program operations
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
•
8M: 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two I/O read mode) structure or 2,097,152 x 4 bits (four I/O
read mode) structure
• 256 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 32 Equal Blocks with 32K byte each
- Any Block can be erased individually
• 16 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Program Capability
- Byte base
- Page base (256 bytes)
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 80MHz with 8 dummy cycles
- 2 I/O: 80MHz with 4 dummy cycles, equivalent to 160MHz
- 4 I/O: 70MHz with 6 dummy cycles, equivalent to 280MHz;
- Fast program time: 1.2ms(typ.) and 3.0ms(max.)/page (256-byte per page)
- Byte program time: 10us (typ.)
- Fast erase time
- 30ms(typ.) and 200ms(max.)/sector (4K-byte per sector)
- 200ms(typ.) and 1000ms(max.)/block (32K-byte per block)
- 500ms(typ.) and 2000ms(max.)/block (64K-byte per block)
- 5.0s(typ.) and 10s(max.)/chip
• Low Power Consumption
- Low active read current: 12mA(max.) at 80MHz, 7mA(max.) at 33MHz
- Low active erase/programming current: 25mA (max.)
- Low standby current: 8uA (typ.)/30uA (max.)
• Low Deep Power Down current: 8uA(max.)
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instruc-
tions
- Additional 4K-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
-
Automatically erases and verifies data at selected sector or block
-
Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first).
P/N: PM1718
Rev. 1.8, October 24, 2017
5
微控制器 MCU
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