100355 Low Power Quad Multiplexer/Latch
July 1989
Revised August 2000
100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of
which can accept and store data from two sources. When
both Enable (E
n
) inputs are LOW, the data that appears at
an output is controlled by the Select (S
n
) inputs, as shown
in the Operating Mode table. In addition to routing data
from either D
0
or D
1
, the Select inputs can force the out-
puts LOW for the case where the latch is transparent (both
Enables are LOW) and can steer a HIGH signal from either
D
0
or D
1
to an output. The Select inputs can be tied
together for applications requiring only that data be steered
from either D
0
or D
1
. A positive-going signal on either
Enable input latches the outputs. A HIGH signal on the
Master Reset (MR) input overrides all the other inputs and
forces the Q outputs LOW. All inputs have 50 k
Ω
pull-down
resistors.
Features
s
Greater than 40% power reduction of the 100155
s
2000V ESD protection
s
Pin/function compatible with 100155
s
Voltage compensated operating range
= −
4.2V to
−
5.7V
s
Available to industrial grade temperature range
Ordering Code:
Order Number
100355PC
100355QC
100355QI
Package Number
N24E
V28A
V28A
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
−
40
°
C to
+
85
°
C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
Pin Names
E
1
, E
2
S
0
, S
1
MR
D
na
–D
nd
Q
a
–Q
d
Q
a
–Q
d
Description
Enable Inputs (Active LOW)
Select Inputs
Master Reset
Data Inputs
Data Outputs
Complementary Data Outputs
28-Pin PLCC
© 2000 Fairchild Semiconductor Corporation
DS010147
www.fairchildsemi.com
100355
Absolute Maximum Ratings
(Note 2)
Storage Temperature (T
STG
)
Maximum Junction Temperature (T
J
)
V
EE
Pin Potential to Ground Pin
Input Voltage (DC)
Output Current (DC Output HIGH)
ESD (Note 3)
−
65
°
C to
+
150
°
C
+
150
°
C
−
7.0V to
+
0.5V
V
EE
to
+
0.5V
Recommended Operating
Conditions
Case Temperature (T
C
)
Commercial
Industrial
Supply Voltage (V
EE
)
0
°
C to
+
85
°
C
−
40
°
C to
+
85
°
C
−
5.7V to
−
4.2V
−
50 mA
≥
2000V
Note 2:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 3:
ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 4)
V
EE
= −
4.2V to
−
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0°C to
+85°C
Symbol
V
OH
V
OL
V
OHC
V
OLC
V
IH
V
IL
I
IL
I
IH
Parameter
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input LOW Current
Input HIGH Current
S
0
, S
1
E
1
, E
2
D
na
–D
nd
MR
I
EE
Power Supply Current
−87
220
350
340
430
−40
mA
Inputs Open
µA
V
IN
=
V
IH (Max)
−1165
−1830
0.50
Min
−1025
−1830
−1035
−1610
−870
−1475
Typ
−955
−1705
Max
−870
−1620
Units
mV
mV
mV
mV
mV
mV
µA
V
IN
=
V
IH (Max)
or V
IL (Min)
V
IN
=
V
IH (Min)
or V
IL (Max)
Guaranteed HIGH Signal
for ALL Inputs
Guaranteed LOW Signal
for ALL Inputs
V
IN
=
V
IL (Min)
Conditions
Loading with
50Ω to
−2.0V
Loading with
50Ω to
−2.0V
Note 4:
The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
3
www.fairchildsemi.com
100355
Commercial Version
(Continued)
PLCC AC Electrical Characteristics
V
EE
= −
4.2V to
−
5.7V, V
CC
=
V
CCA
=
GND
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
TLH
t
THL
t
S
Parameter
Propagation Delay
D
na
–D
nd
to Output
(Transparent Mode)
Propagation Delay
S
0
, S
1
to Output
(Transparent Mode)
Propagation Delay
E
1
, E
2
to Output
Propagation Delay
MR to Output
Transition Time
20% to 80%, 80% to 20%
Setup Time
D
na
–D
nd
S
0
, S
1
MR (Release Time)
t
H
Hold Time
D
na
–D
nd
S
0
, S
1
t
PW
(L)
t
PW
(H)
t
OSHL
Pulse Width LOW E
1
, E
2
Pulse Width HIGH MR
Maximum Skew Common Edge
Output-to-Output Variation
Data to Output Path
t
OSLH
Maximum Skew Common Edge
Output-to-Output Variation
Data to Output Path
t
OST
Maximum Skew Opposite Edge
Output-to-Output Variation
Data to Output Path
t
PS
Maximum Skew
Pin (Signal) Transition Variation
Data to Output Path
Note 5:
Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t
OSHL
), or LOW-to-HIGH (t
OSLH
), or in opposite
directions both HL and LH (t
OST
). Parameters t
OST
and t
PS
guaranteed by design.
T
C
=
0°C
Min
0.60
Max
1.70
T
C
= +25°C
Min
0.60
Max
1.70
T
C
= +85°C
Min
0.70
Max
1.80
Units
Conditions
ns
Figures 1, 2
1.00
2.40
1.00
2.40
1.20
2.50
ns
0.80
0.80
0.60
1.80
2.10
1.30
0.80
0.80
0.60
1.80
2.10
1.30
0.80
0.80
0.60
1.90
2.10
1.30
ns
ns
ns
Figures 1, 3
Figures 1, 2
0.80
1.60
1.40
0.30
−0.10
2.00
2.00
330
0.80
1.60
1.40
0.30
−0.10
2.00
2.00
330
0.80
1.60
1.40
0.30
−0.10
2.00
2.00
330
ns
Figure 4
Figure 3
ns
Figure 4
ns
ns
ps
Figure 2
Figure 3
PLCC only
(Note 5)
PLCC only
370
370
370
ps
(Note 5)
PLCC only
370
370
370
ps
(Note 5)
PLCC only
270
270
270
ps
(Note 5)
5
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