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100354

产品描述Low Power 8-Bit Register with Cut-Off Drivers
文件大小91KB,共9页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
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100354概述

Low Power 8-Bit Register with Cut-Off Drivers

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100354 Low Power 8-Bit Register with Cut-Off Drivers
October 1989
Revised August 2000
100354
Low Power 8-Bit Register with Cut-Off Drivers
General Description
The 100354 contains eight D-type edge triggered, master/
slave flip-flops with individual inputs (D
n
), true outputs (Q
n
),
a clock input (CP), an output enable pin (OEN), and a com-
mon clock enable pin (CEN). Data enters the master when
CP is LOW and transfers to the slave when CP goes HIGH.
When the CEN input goes HIGH it overrides all other
inputs, disables the clock, and the Q outputs maintain the
last state.
A Q output follows its D input when the OEN pin is LOW. A
HIGH on OEN holds the outputs in a cut-off state. The cut-
off state is designed to be more negative than a normal
ECL LOW level. This allows the output emitter-followers to
turn off when the termination supply is
2.0V, presenting a
high impedance to the data bus. This high impedance
reduces termination power and prevents loss of low state
noise margin when several loads share the bus.
The 100354 outputs are designed to drive a doubly termi-
nated 50
transmission line (25
load impedance). All
inputs have 50 k
pull-down resistors.
Features
s
Cut-off drivers
s
Drives 25
load
s
Low power operation
s
2000V ESD protection
s
Voltage compensated operating range
= −
4.2V to
5.7V
s
Available to industrial grade temperature range
Ordering Code:
Order Number
100354PC
100354QC
100354QI
Package Number
N24E
V28A
V28A
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
40
°
C to
+
85
°
C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
Pin Names
D
0
–D
7
CEN
CP
OEN
Q
0
–Q
7
Description
Data Inputs
Clock Enable Input
Clock Input (Active Rising Edge)
Output Enable Input
Data Outputs
28-Pin PLCC
© 2000 Fairchild Semiconductor Corporation
DS010610
www.fairchildsemi.com

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